近年來半導體工業朝向發展體積小、低消耗功率、低漏電流以及高操作速度的元件與系統發展。 SOI 元件為新興的半導體技術具有許多獨特的特性,是朝此方向發展最有希望的技術之ㄧ。而在半導體記憶體方面,利用PD-SOI nMOSFET的浮體效應所做成的單電晶記憶體可以使記憶體的面積大大的縮小。在本篇論文我們提出一新結構的 1T DRAM cell , 此元件可利用其環繞在 body 四周特有的BLOCK OXIDE來降低元件集級/源極與本體間的接面電容。並且利用此元件結構上的特性,可以大大提升 DRAM cell 的 programming 達80 % 以上。


在製程上，我們運用NDL（國家奈米實驗室）的機台設備來實際做出這項元件。在製作上技術上，我們並非用SOI 晶圓去完成我們新架構的元件而是直接在bulk的晶片上成長buried oxide後再沉積出Si薄膜,以類似 TFT(thin film transistor )的方法來完我們的元件,但自行沉積完成的矽薄膜層是由許多不同 Crystal Orientation 的 Single Crystal of Silicon Grains 所組成之純矽物質，所以有著比單晶矽薄層更多的晶格間隙跟不固定的能階，在品質跟薄膜厚度上都比較不穩定，邊晶現象會相當嚴重，所以元件製作的失敗率較高,但我們還是成功製作出此元件。因此如果能廣泛將元件以這種類似TFT的形式完成,由於不需要使用SOI 晶圓 ,則可大大降低成本。

Recently the semiconductor industry tends to develop a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. SOI technology having many unique characteristics is one of the most hopeful methods in the direction. As semiconductor memory is concerned, The 1T-DRAM cell realized by the concept of floating body effect in a PD-SOI nMOSFET, that can allow DRAM cell to be scaled down in depth with less area occupied .In this paper, we will propose a new structure of 1T-DRAM cell, which has the buried oxide and block oxide around its body. It can suppress the junction capacitor between the S/D and the body of the cell. In addition it can also improve the programming window of the 1T-DRAM cell more than 80% by utilizing its own structural characteristic.

We fabricated our new device in National Nano Device Laboratories. The device was carried out by depositing oxide and poly film on bulk Si wafer, just like TFT process. But doing by this way it has some issues about the polycrystalline channel and the S/D. Although it has some issues, but we made it successful using bulk Si wafer rather than expensive SOI wafer. It indeed reduces the cost of process.

第一章 緒論 1
第二章 現有 SOI CAPACITOR-LESS DRAM 元件的種類與概述 4
2-1 CAPACITOR LESS DRAM (CDRAM) 4
2-2 Double gate 1T DRAM cell 6
2-3 GATE INDUCED DRAIN LEAKAGE (GIDL) 1T DRAM CELL 7
2-4 FLOATING BODY 1T DRAM CELL (FBC) 9
2-5 Twin transistor random access memory (TTRAM) 12

第三章 新元件結構的模擬 14
3-1 四種元件(CMP-BMPI DEP-BMPI CMP-BSOI DEP-BSOI)結構說明 14
3-2 四種元件(CMP-BMPI DEP-BMPI CMP-BSOI DEP-BSOI)的電性模擬15
3-3 新元件架構的探討分析 21
3-4 變化結構參數比較整理與結論 22
第四章 新元件結構的設計與製作 27
4.1 製作BMPI BODY 27
4.2 製作BMPI BLOCK OXIDE 34
4.3 製作BMPI SOURCE與 DRAIN 36
4.4 元件隔離及完成主動區域 37
4.5 製作BMPI GATE 與 GATE OXIDE 39
4.6 製作Contact Hole 42
4.7 製作金屬層 44

第五章 實驗結果量測與討論 46
5-1 IDS － VDS 特性曲線 47
5-2 結論 50
第六章 結論與未來發展 52

Reference 53
附錄 A: 投稿的會議論文 57

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