本論文提出運用運算放大器(OP-Amp)完成之積分器來達成切換電流式三角積分調變器之設計，文中所探討的內容包含利用運算放大器來降低輸入阻抗並達到高速及高解析度之目的，並提出利用虛開關串疊式架構來減少交換式電流電路中之非理想效應。在電路實現方面，提出一個利用運算放大器及具有虛開關之串疊式架構回授電路來設計出離散積分器，以應用在三角積分調變器中。
在系統電路的實現上，我們採用TSMC 0.35μm的互補式金氧半導體(CMOS)製程參數進行模擬；採用二階一位元單迴路式的架構，在取樣頻率為10.24MHz、超取樣率為128、消耗功率為21mW的條件下，可得到最大訊號雜訊與失真比為72dB，且具有大於70dB的動態範圍。
在電路設計上，主要針對切換電流式取樣電路之架構及特性加以分析，其後再依系統方塊依序描述與探討，並以Cadence hspice模擬軟體驗證其功能。

In this thesis, a switched-current sigma-delta modulator (SDM) with op-amp active integrator is proposed. The major study is focused on using the op-amp to reduce the input impedance for high speed and high solution and utilizes the dummy switch to decrease the clock feedthrough (CFT) error. We use a sample-and-hold circuit which consists of an op-amp active memory cell and a dummy switch circuit to implement the integrator. It is applied to the building blocks of SDM.
The modulator is a second order sigma-delta modulator. A current comparator transforms the current signal into digital voltage signal. A single-bit digital-to-analog (D/A) feedback circuit is used to convert the one-bit digital output to the SI integrator .The modulator is designed in the current mode technique.
The delta-sigma modulator simulates using the parameters of the TSMC 0.35μm CMOS process. The simulation results show that the signal to noise plus distortion ratio (SNDR) is 72 dB, the sampling rate is 10.24MHz, the oversampling ratio is 128, the power consumption is 21mW, the dynamic range is about 70dB, and the power supply is 3.3V.
Furthermore, the circuit is verified by cadence-hspice simulation.

Chapter 1 Introduction………………………………………………………………….1
1.1 Research Motivation....................................................................................1
1.2 Chapter and Organization ...........................................................................3

Chapter 2 The Architectures and Algorithms of Sigma-Delta Modulator…………...4
2.1 Sample and Hold (S/H) Circuit....................................................................4
2.2 Analog to Digital Converter (ADC) Introduction ....................................5
2.3 Operating Principle of Analog to Digital Converter (ADC)………………7
2.3.1 Nyquist-Rate ADC…………………………………………………..7
2.3.2 Oversampling ADC………………………………………………..13
2.3.3 Sigma-Delta ADC (Σ - Δ ADC) : Noise Shaping………………….16

Chapter 3 Sample / Hold Circuit………………………………………………………23
3.1 Sample and Hold Circuit............................................................................23
3.2 Switched-Current Circuit...........................................................................24
3.3 Non-Ideal Behavior....................................................................................25
3.3.1 Mismatch ..........................................................................................25
3.3.2 Transmission Error ...........................................................................27
3.3.3 Clock Feedthrough (CFT) error........................................................29
3.3.4 Noise.................................................................................................33
3.4 Compensation of Non-Ideal Behavior.......................................................35

Chapter 4 Design of the Proposed Second-Order SI Sigma-Delta Modulator ..........40
4.1 Integrator....................................................................................................40
4.1.1 Current Memory Cell........................................................................41
4.1.2 Delay Cell.........................................................................................42
4.1.3 Non-inverting Integrator...................................................................42
4.1.4 Proposed OP-Amp Active Memory Cell .........................................44
4.1.5 Proposed Op-Amp Active Integrator................................................49
4.2 Quantizer....................................................................................................51
4.3 Digital to Analog Converter (DAC)……………………………………..51
4.4 The Proposed SDM Circuit………………………………………………52

Chapter 5 Simulation Results of the Proposed Second-Order SI Sigma-Delta Modulator.......................................................................................................54
5.1 Proposed OP-Amp Active Integrator.........................................................54
5.2 Quantizer....................................................................................................57
5.3 Digital to Analog Converter (DAC)..........................................................58
5.4 Proposed Second-Order Sigma-Delta Modulator......................................58

Chapter 6 Conclusion…………………………………………………………………..63
Reference………………………………………………………………………………..64

[1] D. L. Fried, “Analog Sample-Data Filters”, IEEE J. Solid-State Circuits, Vol. SC-7, pp. 302-304, Aug. 1972.
[2] J. B. Hughes, N. C. Bird, and Lan C. Macbeth, “Switched Current – A New Technique for Analog Sample-Data Signal Processing”, IEEE International Symposium on Circuits and Systems, pp. 1154-1187, 1989.
[3] H. C Yang, T. S. Fiez, D. J. Allstot, “Current-Feedthrough Effects and Cancellation Techniques in Switched-Current Circuits”, Proc. Of Int. Symp. Circuits And Systems (ISCAS), New Orleans, IEEE, pp. 3186-3188, May 1990.
[4] T. S. Fiez, D. J. Allstot, G. Liang, and P. Lao, “Signal-Dependent Clock-Feedthrough Cancellation in Switched-Current Systems”, Circuits And Systems, Shenzhen, China, IEEE, pp. 785-788, June 1991.
[5] M. Song, Y. Lee, and W. Kim, “A Clock Feedthrough Reduction Circuit for Switched-Current Systems”, IEEE J. Solid-State Circ., Vol. 28, No. 2, pp. 133-137, Feb. 1993.
[6] M. Helfenstein, and G. S. Moschytz, “Improved Two-Step Clock-Feedthrough Compensation Technique for Switched-Current Circuits”, IEEE Trans. On CAS-II, Vol.45, No. 6, pp. 739-743, June 1998.
[7] D. Macq and P. Jespes, “Charge Injection in Current-Copier Cells”, Electron. Lett., Vol. 29, No. 9, pp. 780-781, Apr. 1993.
[8] M. Loulou, D. Dallet and P. Marchegay, “A 3.3V Switched-Current Second Order Sigma-Delta Modulator for Audio Applications”, ISCAS 2000 - IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, pp. IV-409-IV-412, May 28-31, 2000.
[9] R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Volume II, IEEE Inc., 2002.
[10] D. A. Johns and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, Inc.,1997.
[11] Mikael Gustavsson, J. Jacob Wikner and Nianxiong Nick Tan, CMOS Data Converters For Communications, Klower Academic Publishers, Boston, 2000.
[12] Yves Geerts, Michiel Steyaert and Willy Sansen, Design of Multi-Bit Delta-Sigma A/D Converters, Klower Academic Publishers, Boston, 2002.
[13] Bengt E. Jonsson, Ericsson Radio Syatems AB, Switched-Current Signal Processing and A/D Conversion Circuits : Design and Implemintation, Klower Academic Publishers, Boston, 2000.
[14] Behzad Razavi, Design of Analog CMOS Integrated Circuit, McGraw-Hill, New York, 2001.
[15] Nianxiong Tan, Switched-Current Design and Implementation of Oversampling A/D Converters, Klower Academic Publishers, 1997.
[16] J. B. Hughes, and K. W. Moulding, “S2I: A Two-step Approach to Switched-Currents”, IEEE Proc. Of Int. Symp. ISCAS, Chicago, Illinois, pp. 1235-1238, May 1993.
[17] C.Toumazou, J. B. Hughes, and N. C. Battersby, Switched-Currents an analogue technique for digital technology, IEE Circuits, Devices and Systems Series, 1993.
[18] D. G. Nairn, and C. A. Salama, “Current mode analog-to-digital converters”, Proc. IEEE International Symposium on Circuits and Systems, pp. 1588-1591, May 1989.
[19] D. Vallancourt, Y. P. Tsividis and S. J. Daubert, “Sampled-current circuits”, Proc. IEEE International Symposium on Circuits and Systems, pp. 1592-1595, May 1989.
[20] H. Traff, “Novel approach to high-speed CMOS current comparators”, Electron. Lett., 28, pp. 310-2, Jan. 1992.
[21] R. Jacob Baker, Harry W. Li, and David E. Boyce, CMOS circuit design, layout, and simulation, IEEE Inc., 1997.
[22] R. Rodriguez-Calderon, J. Santana-Corte, and F. Sandoval-lbarra, “Reducing Non-Idealities on Switched-Current Sigma-Delta Modulators”, Fourth IEEE International Caracas Conference on Devices, Circuits and Systems, Aruba, pp. C019-1-C019-5, April 17-19, 2002.
[23] Guo-Ming Sung, Kuo-Hsuan Chang, and Wen-Sheng Lin, “A 12-B 10-Msamples/s CMOS Switched-Current Delta-Sigma Modulator”, ©IEEE, pp. 5573-5576, 2005.
[24] Wen-Sheng Lin, The design of Switched-Current Delta-Sigma Modulator, Master thesis, National Taipei University of Technology, 1, Sec. 3, Chung-Hsiao E. Rd., Taipei 106, Taiwan, 2004.