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論文名稱 Title |
採用CMOS準指數電路之對數領域濾波器 A Log-Domain Filter Based On CMOS Pseudo-Exponential Circuit |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
60 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2008-07-30 |
繳交日期 Date of Submission |
2008-07-31 |
關鍵字 Keywords |
對數領域濾波器、飽和區 log-domain filter, saturation region |
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統計 Statistics |
本論文已被瀏覽 5694 次,被下載 0 次 The thesis/dissertation has been browsed 5694 times, has been downloaded 0 times. |
中文摘要 |
本論文提出一個使用pseudo-exponential方程式與飽和區操作金氧半電晶體的CMOS可調式二階對數領域濾波器。與雙載子電晶體BJT或弱轉換金氧半電晶體濾波器相比,擁有較高的工作頻率。 在本研究中使用 0.35um CMOS 製程製作晶片,供應電壓為3V,內建電容為1pF,調整電流為2uA~10uA,截止頻率為2MHz~37.5MHz,總諧波失真為0.93%,功率損耗為772uW。 |
Abstract |
In this thesis, a CMOS tunable second-order log-domain filter using pseudo-exponential approximation is proposed. MOSFETs in the circuit are working in the saturation region. This filter has higher frequency response than that of weak inversion CMOS filter. The circuit has been fabricated with 0.35um CMOS technology. It operates with a supply voltage 3V, internal capacitance C is 1pF, the biasing current varies from 2uA~10uA. The cutoff frequency can be turned from 2MHz~37.5MHz. The harmonic distortion is 0.93% and the power consumption is 772uW. |
目次 Table of Contents |
Abstract Chapter 1 Introduction 1 1.1 Background 1 1.2 Companding Filter 2 1.3 Motivation 4 1.4 Thesis Organization 5 Chapter 2 Previous Log Filter 6 2.1 Adams’s Log Filter Circuit 6 2.2 BJT Log-Domain Filter 9 2.3 Lateral Bipolar Transistor Log-Domain Filter For CMOS 11 2.4 CMOS Weak Inversion Log-Domain Filter 13 2.5 SRD filter 16 2.6 The Pseudo-Exponential Filter 18 2.6.1 Positive Transconductor 18 2.6.2 Negative Transconductor 20 2.6.3 The First-Order Filter 21 2.6.4 The Second-Order Filter 23 Chapter 3 The Proposed Circuit 25 3.1 Positive Transconductance 25 3.2 Negative Transconductance 26 3.3 The Proposed Second-Order Log-domain Filter 27 3.3.1 Input Circuit 29 3.3.2 Output Circuit 31 3.4 Transfer Function 32 Chapter 4 Simulation and Measurement Results of the Proposed Second-Order Log Filter 36 4.1 The Circuit Implement, Layout& Specifics 36 4.2 Testing method & Measurement circuit 39 4.3 Frequency Response 40 4.4 Time response 42 4.5 Tunable Range 45 4.6 Total Harmonic Distortion 46 4.7 Comparisons 47 Chapter 5 Conclusion 49 References 50 |
參考文獻 References |
[1] Y. Tsividis, “Externally linear time-invariant systems and their applications to companding signal processors”, IEEE TCAS-II, vol. 44, no. 2, pp. 65-85, Feb. 1997. [2] R. W. Adams, “Filtering in the log-domain”, In 63rd AES Conf., New York, 1979. [3] D. R. Frey, “Log-domain filtering: an approach to current-mode filtering”, IEE Proc. G, vol. 140, pp. 406-416, 1993. [4] D. R. Frey, “Exponential state space filters: A generic current mode design strategy”, IEEE Trans. Circuits Syst. I, vol. 43, pp. 34-42, Jan. 1996. [5] C. Toumazou, J. Ngarmnil and T. S. Lande, “Micropower log-domain filter for electronic cochlea”, Electronics Letters, Vol. 30 No. 22, pp. 1839-1841, 27th Oct. 1994. [6] N. Krishnapural, Y. Tsividis, “A Micropower Log-Domain Filter Using Enhanced Lateral PNPs in a 0.25 um CMOS Process”, Symposium on VLSI Circuits Digest of Technical Papers, pp.179~182, June 2001. [7] J. Mulder, A.C. van der Woerd, W.A. Serdijn and A.H.M. van Roermund, “Current-mode companding √x domain integrator”, Electronics Letters, Vol. 32 Issue 3, pp. 198-199, Feb. 1996. [8] C.A. De La Cruz-Blas, A.J. Lopez-Martin and A. Carlosena, “1.5V tunable Square-Root Domain filter”, Electronics Letters, Vol. 40 No. 4, pp. 213-214, 19th Feb. 2004. [9] Q. H. Duong, T. K. Nguyen, H. N. Duong, S.G. Lee, “Ultra low-voltage and low-power dB-linear V-I converter using composite NMOS transistors”, IEEE Electron Devices and Solid-State Circuits, pp. 101-104, Dec. 2003. [10] Q. H. Duong, S.G. Lee, “A low-voltage low-power high dB-linear and all CMOS exponential V-I conversion circuit”, IEEE Digest of Papers, pp. 683–686, June 2005. [11] D. Frey, “C-LOG DOMAIN FILTERS”, IEEE/Digital Object Identifier 10.1109/ISCAS, Vol. 1 No. 28-31, pp. 176-179, May 2000. [12] W. Himmelbauer, A.G. Andreou, “Log-Domain Circuits in Subthreshold MOS”, The 40th Midwest Symposium on Circuits and Systems, CAS, vol. 1, pp. 26-30, 3-6 Aug. 1997. [13] G. J. Yu, B.D. Liu, Y.C. Hsu, and C.Y. Huang, “Design of log domain low-pass filters by MOSFET square law”, The Second IEEE Asia Pacific Conf. on ASICs, pp. 9-12, 28th-30th Aug. 2000. [14] N.S. Nise, “Control Systems Engineering”, Reading, MA:Addison-Wesley, 1995. [15] E.M. Drakakis, A.J. Payne and C. Toumazou, “Log-domain filtering and Bernoulli cell”, IEEE Trans. Circuits and Systems I, Vol. 46 No. 5, pp. 559-571, May 1999. [16] A.J. Lopez-Martin, C.A.D.L.C. Blas, A. Carlosena, “1.2-V 5u/W class-AB CMOS log-domain integrator with multidecade tuning”, IEEE Trans. Circuits and Systems II, Vol. 52 Issue 10, pp. 665-668, Oct. 2005. [17] J. Veerendra Kumar and K. Radhakrishna Rao, ”A Low-Voltage Low Power CMOS Companding Filter”, in Proc. 16th Int. Conf. on VLSI Design, pp. 309-314, 4th-8th Jan. 2003. |
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