本篇論文設計了一個低功率消耗與低相位雜訊全積體化除整數之頻率合成器，並利用充放電電流幫浦架構的鎖相迴路來組成。本頻率合成器主要應用於IEEE 802.16b WiMAX 5.725GHz至 5.825GHz免執照頻段，提供5.13GHz至5.22GHz的本地振盪器，並應用於射頻收發機的前端電路。本論文的頻率合成器包含相頻偵測器(PFD)、電荷幫浦(CP)、低通迴路濾波器(LPF)、壓控振盪器(VCO)以及含雙模數前置除頻器(dual-modulus prescaler)之pulse-swallow divider。電路設計中以新的架構來達到低功率消耗與低相位雜訊的壓控振盪器效能；而在除頻器方面並採用最佳化E-TSPC架構，使得除頻器可操作在維持高頻區且大幅降低功率的耗損。此頻率合成器採用TSMC 0.18μm 1P6M CMOS製程，整個晶片面積為1.1 mm2。

This thesis presents a low power consumption and low phase noise CMOS integer-N frequency synthesizer, and it bases on a charge-pump PLL topology. The frequency synthesizer can be used for IEEE 802.16b unlicensed band of WiMAX(World Interoperability for Microwave Access) from 5.725GHz to 5.825GHz. It provides the one ration frequency ranged from 5.13GHz to 5.22GHz for the local oscillator in RF front-end circuits. The proposed frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage-controlled oscillator, and a pulse-swallow divider. In system design, we present the new architecture for voltage-controlled oscillator to achieve low power consumption and low phase noise. Moreover divider is implemented by an optimal extended true single-phase clock-base prescaler. It can achieve high-resolution frequency operation and reduction of power consumption. This chip is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The whole chip area is 1.1 mm2.

CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 4
CHAPTER 2 THE CONCEPTS OF FREQUENCY SYNTHESIZER 5
2.1 RF Front-end Circuit 5
2.1.1 Phase noise, Spurs, and Lock time 6
2.1.2 Specification of frequency synthesizer fot WiMAX 6
2.2 Types of Frequency Synthesizer 8
2.2.1 The Digital Synthesizer 8
2.2.2 The Direct Synthesizer 10
2.2.3 The Indirect Synthesizer 11
2.3 Frequency Synthesizer 12
2.3.1 Basic Concepts 12
2.3.2 Voltage-Controlled Oscillator 13
2.3.3 Phase Frequency Detector (PFD) 17
2.3.4 Charge Pump and Loop Filter 21
2.3.5 Frequency Divider 23
CHAPTER 3 The Proposed Frequency Synthesizer 26
3.1 Introduction 26
3.2 VCO (voltage controlled oscillator) 28
3.2.1 Cross-coupled LC VCO 28
3.2.2 The proposed LC VCO 30
3.3 Frequency Divider 36
3.3.1 High speed prescaler 38
3.3.2 Dual-modulus prescaler 39
3.4 Phase-Frequency Detector 40
3.5 Charge Pump 41
3.6 Loop filter 42
CHAPTER 4 SIMULATION RESULT 43
4.1 RF Model and CMOS process 43
4.2 Simulation of VCO 43
4.2.1 Performance of VCO 46
4.3 Simulation of Frequency divider 47
4.4 Simulation of PFD and CP 51
4.5 Simulation of Frequency Synthesizer 52
4.6 Layout of Chip 60
CHAPTER 5 MEASUREMENT RESULT 61
5.1 Measurement result 61
CHAPTER 6 CONCLUSION AND FUTURE WORK 65
6.1 Conclusion 65
6.2 Future Work 65
Reference 66

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