傳統的CMOS製程下，耦合器採矽基金屬堆疊結構，該金屬堆疊結構在高頻時所產生之寄生電容會引起能量損失，元件之高頻訊號也容易由基板流失，兩者皆為造成高插入損耗的主要原因。除了上述CMOS製程之耦合器，目前亦有運用單晶微波積體電路(MMIC)所開發之耦合器，該耦合器雖然具有四相位輸出設計的元件，然而元件面積較大，難整合於大型積體電路中[1]。為了改善上述兩種製程之缺點，本論文提出運用微機電系統技術(MEMS)，設計具有懸浮架構之四相位輸出耦合器，達到降低能量耗損以及縮小元件面積之目的。
為使耦合器具有低損耗、四相位輸出與高隔離度之特性，本論文對於製程整合與元件結構設計提出以下三種方法：(i)藉懸浮式結構之設計減少基板與元件間寄生電容引起之能量損失；(ii)加入介電層為空氣之MIM電容進行端埠匹配；(iii)採用串聯耦合器搭配中央抽頭式巴倫器產生四相位輸出，並運用高頻模擬軟體(HFSS及ADS)進行元件最佳化模擬及分析。本論文所開發之耦合器元件結構由支撐銅柱、耦合器主結構(下電極)、耦合層銅柱(介電層)、走線連接及共地(上電極)共四層堆疊銅金屬層所組成，製程包括四次薄膜沉積、四次黃光微影之圖形定義、三次銅種子層蒸鍍、四次銅電鍍沉積及一次去除犧牲層釋放結構之製程。
本實驗室前期研究成果(許文宏學長，2014)顯示，該四相位耦合器面積為22 mm(W) × 12.8 mm(L) × 71 µm(H)，運用MEMS面型微加工製程技術研發製作；在類似的製程條件下，相較於第一代元件，本論文所完成之第二代懸浮式四相位耦合器元件，面積大幅減少為9.5 mm(W) × 6.4 mm(L) × 36 µm(H)，且四輸出端埠插入損耗特性可由-45.0 dB、-47.9 dB、-49.8 dB、-51.6 dB分別降低至-18.74 dB、-20.14 dB、-24.10 dB、-22.23 dB，整體插入損耗約改善56 %；輸入反射損耗由-4.53 dB降低為-15.08 dB，反射損耗之高頻特性提升約3.3倍；另外，相對於相位標準值(180°)，兩輸出端埠相位標準差值分別由16.1°與21.1°改善至1.2°與4.7°。

The conventional coupler realized by utilizing CMOS process with stacked structure, this stacked layers will increase the insertion loss due to the parasitic capacitance and lossy substrate in radio-frequency. Except the CMOS process, there are also couplers with four-phase output characteristic implemented in Monolithic Microwave Integrated Circuit (MMIC) manufacturing process. However, MMIC couplers are difficult to integrate with ICs since it consumes larger area[1]. In order to overcome the above mentioned issues, this thesis proposes the suspended four-phase output coupler using Micro-Electro-Mechanical Systems (MEMS) process to enhance the insertion loss and reduce the dimension of the traditional coupler.
To achieve the four-phase coupler with low insertion loss, four-phase output and high isolation characteristics, the main fabrication processes in this thesis including: (i) Utilize suspended structure to enhance the insertion loss caused by parasitic capacitance between device and substrate; (ii) Use the air dielectric layer of MIM capacitors for input/output ports matching; (iii) Construct of a tandem coupler with center-tapped baluns to perform four-phase output, and optimize the analysis of the coupler by employing high frequency simulation software (HFSS and ADS. The suspended four-phase coupler constructed of supported posts, bottom and top electrodes and vias. The main fabrication processes including four thin-film depositions, four photolithography, four copper electroplating and etching processes.
Our previous research (Wen-Hong Hsu, senior, 2014) had developed a first-generation four-phase coupler using MEMS surface micromachining process with dimensions of 22 mm (W) × 12.8 mm (L) × 71 μm (H); under the similar processing conditions, the second-generation of suspended four-phase coupler in this thesis is significantly smaller than first-generation one with size of 9.5 mm (W) × 6.4 mm (L) × 36 μm (H). Compare the characteristic of insertion loss with the first-generation, which enhanced from -45.0, -47.9, -49.8 and -51.6 dB, to -18.74, -20.14, -24.10 and -22.23 dB, is approximately 56% improvement of insertion loss. Input return loss of -4.53 dB is improved to -16.20 dB, which shows characteristic of reflection loss boosting about 3.5 times. In addition, compared to the standard phase difference (180°), the output of two-port phase difference respectively improved from 16.1° and 21.1° to 1.2° and 4.7°.

論文審定書 i
誌謝 iii
摘要 iv
Abstract v
目錄 vii
第一章 緒論 1
1.1前言 1
1.2研究動機與背景 2
1.3論文架構及實驗方法 4
第二章 方向耦合器理論簡介與分析 5
2.1耦合線(Coupled-Line)方向耦合器與奇偶模分析 5
2.2正交耦合器簡介分析 10
2.2.1分支線(Branch-Line)耦合器 10
2.2.2藍基(Lange)耦合器 14
2.3反相耦合器簡介分析 16
2.3.1鼠競(Rat-Race)耦合器 16
2.3.2巴倫器(Balun) 19
第三章 耦合器之模擬設計與製作 20
3.1耦合器之特性指標 21
3.3懸浮式反相巴倫器特性模擬 27
3.4懸浮式四相位耦合器特性模擬 31
3.5懸浮式四相位耦合器之光罩佈局設計 34
3.6懸浮式四相位耦合器之製程整合 35
3.7懸浮式四相位耦合器之製程步驟及參數 36
第四章 實驗結果與討論 47
4.1銅結構之電鍍沉積技術 47
4.2懸浮式四相位耦合器之高頻特性量測 49
4.2.1初始結構量測結果與討論 50
4.2.2改良後結構之量測結果與討論 52
4.2.3與前代元件之比較與檢討 56
4.2.4檢討後修正參數模擬驗證 59
第五章 結論與未來展望 63
5.1結論 63
5.2未來展望 64
參考文獻 65

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