隨著半導體先進製程的發展，電路能夠以更小的面積被實現，但電路在製造時也因此更容易的受到製造缺陷(defect)以及製程飄移(process variation)的影響，使得晶片無法順利運作。而即使能夠確保晶片在出廠時能夠正常運作，晶片也會隨著使用而老化、劣化並產生錯誤。此外在電路運作時，也可能因為宇宙帶電粒子的碰撞，使得電路產生軟性錯誤(soft error)，進而影響到系統的可靠度。
邏輯隱含(implication)則是在近幾年被提出的一種新的即時偵錯方法，用以提升系統的可靠度與可診斷性。其核心概念在於電路當中邏輯閘間的輸入輸出線可能會存在固定不變的關係，以及(AND)閘為例，當任意一個輸入為邏輯準位0時，輸出則為邏輯準位0，此關係被稱為一組邏輯隱含。因此只要加入額外的錯誤檢查邏輯(error checking logic)來驗證此關係是否成立，便能夠得知電路是否存在錯誤(fault)，當有偵測到電路有錯時，則令錯誤指示訊號(error indication signal)為邏輯準位1，令電路重新執行或者是啟動修復的動作。然而，電路之中可能存在著許多的邏輯隱含關係，為了實現所有邏輯隱含的錯誤檢查電路以及錯誤指示訊號的壓縮電路極可能額外增加許多電路成本。
基於邏輯隱含即時偵錯方法，本論文提出一壓縮技術能夠有效率地減少錯誤指示訊號的數量。我們發現到邏輯隱含間存在著等效以及支配的關係，此種關係相當有利於錯誤指示訊號的壓縮。因此我們發展出了一套有系統的流程能夠有效的找出這類關係，並利用此關係來合併邏輯隱含，且不會對即時偵錯能力造成任何影響。但此壓縮技術有可能會影響電路的可診斷性，因此我們額外開發出一診斷感知壓縮技術，透過犧牲部份壓縮能力以維持電路可診斷性。
我們使用了ISCAS’85與ITC’99共19個電路來評估提出方法的效果，而根據實驗結果，在不考慮電路可診斷性的情況下，提出之壓縮技術平均能夠減少48.49%的錯誤指示訊號。並且進而使錯誤檢查電路與壓縮電路的面積成本分別減少39.23%與34.52%。而在考慮可診斷性的情況下，此壓縮方法平均能夠減少48.23%的錯誤指示訊號，並使錯誤檢查電路與壓縮電路的面積成本分別減少38.82%與34.32%。

Due to the development of advanced semi-conductor process, the circuit in a chip could be implemented with a smaller size. However, chips may thus tend to fail because of the defects and process variation during manufacturing. Even if a chip is verified to work successfully, it might detiorate and cause errors as a result of aging. Also, it is possible that soft errors caused by cosmic rays or thermal neutrons would temporarily change the function of a chip and make the system crash. All these reasons may affect the reliability of a system.
In recent years, a new on-line test method called implication-based concurrent error detection has been proposed for enhancing reliability and diagnosibility enhancement of a system. Implications are the inherent invariant relationships between the inputs or outputs of logic gates in a circuit. Based on implications, we can add corresponding checking logic to test a target circuit by examining whether the implications are still valid or not. If any one employed implication is violated due to errors, an error indication signal will be activated. However, there might exist a large number of implications in a circuit, which may incur quite high hardware overhead.
In this thesis we propose a signal collapsing technique to effectively reduce the number of implication-based error indication signals. We find that there exist equivalent and dominant relationships between the implicants of implications, which are very helpful for collapsing error indication signals. A systematical flow is thus developed to identify these relationships and accordingly merge the implications without sacrificing error detectability. One possible issue is that some diagnnosability loss may also thus incurred. Thus, we further develop a diagnosis-aware collapsing technique for error indication signals. By sacrificing little signal collapsing rate, we could guarantee no diagnosability loss.
In order to evaluate the effectiveness of the proposed technique, our technique is applied to 19 ISCAS’85 and ITC’99 benchmark circuits. The experimental results show that our proposed technique reduces 48.49% error indication signals on average if diagnosability is not concerned, which leads to 39.23% and 34.52% averaged area overhead reduction to the implication checking logic and the OR-tree based compactor circuit, respectively. If diagnosability is considered, our proposed technique can achieve 48.23% reduction on error indication signals on average. 39.23% and 34.52% area overhead reduction is thus achieved on implication checking logic and the compactor, respectively.

論文審定書 i
致謝 ii
摘要 iv
Abstract vi
目錄 viii
圖目錄 x
表目錄 xii
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究貢獻 6
1.3 論文大綱 7
第二章 研究背景及相關文獻探討 8
2.1 邏輯隱含 8
2.2 錯誤模型 10
2.3 傳統壓縮電路之特性說明 12
2.3.1 X-Compact 13
2.3.2 Multiple Input Signature Register(MISR) 15
2.4 偵測機率(Probality of Detection) 17
2.5 電路之可診斷性(Diagnosability) 19
第三章 應用於邏輯隱含即時偵錯方法之錯誤指示訊號壓縮技術 22
3.1 邏輯隱含合併流程 22
3.1.1. 步驟一：辨認電路中之邏輯隱含 23
3.1.2. 步驟二：尋找SH-I, EQ-I, DO-I 24
3.1.3. 步驟三：選擇適當的EQ-I與DO-I 30
3.1.4. 步驟四：評估效益 35
3.2 實現合併後之邏輯隱含的檢查電路 35
第四章 實驗結果分析 37
4.1. 執行時間 37
4.2. Signal Collapsing Rate(SCR) 39
4.3. Probability of Detection(Pdetection) 41
4.4. 邏輯隱含檢查電路之成本 43
式6 43
4.5. OR-Tree壓縮電路之成本 45
4.6. 電路總體面積比較 47
4.7. 電路之可診斷性結果 49
第五章 診斷感知錯誤指示訊號壓縮技術 52
5.1. 可診斷性下降原因之分析 52
5.2. 提出改善電路可診斷性之方法 54
5.3. 電路之可診斷性結果 59
5.4. Signal Collapsing Rate 61
5.5. 電路實現成本分析 63
第六章結論 64
參考文獻 65

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