隨著科技的不斷進步，物聯網(Internet of Things, IoT)的發展更是日新月異，各式各樣的多媒體應用也愈趨廣泛。智慧汽車以及車聯網系統亦為近年來重要的物聯網發展，其中影像處理電路更是其重要的環節之一，舉凡行人辨識、道路辨識、號誌辨識等等皆為影像處理電路的標準應用，隨著普及性與使用率的提高，此電路的可靠度與穩定度也日趨重要。但由於影像處理電路可能會隨著時間老化或因外部環境因素導致內部電路產生錯誤而無法正常運作，以致於產生出來的影像模糊不清甚至無法辨識，進而產生安全上的隱憂。
近年來，容誤的概念被提出，這個概念是基於人類知覺感官對於影像、視訊、音訊中較微小的錯誤並不易察覺，以此來界定該類型的錯誤為在人類可接受範圍內。我們將此概念應用在影像處理電路當中，當影像處理電路中發生錯誤時，其輸出並不一定會完全無法辨識，只要產生的錯誤影像為可辨識物件或可被人類視覺感官所接受，那麼該電路就可以繼續使用，不需要進一步維修或是汰換，如此一來，便能夠減少電路的維護成本並延長其使用壽命。
在本篇論文中，基於容誤的概念之下我們提出一個適用於影像處理電路之無參考測試方法。在這個方法當中，我們只需要利用目標影像中的錯誤特徵進行影像的品質評估，而不需要使用原始的參考影像作為比較，因此我們完全不需要使用額外的記憶體空間來存放參考影像，以此來大幅降低測試電路的硬體面積。除此之外，由於不需要參考影像作為影像品質評估的基準，我們可以直接利用影像處理電路目前所讀取到的影像內容進行即時的影像品質評估。以目前文獻上的容誤測試方法來說，本論文是第一個使用無參考之容誤偵測方法進行影像品質的偵測。我們總共採用了1,004,232張具有不同錯誤特徵的測試影像來驗證此方法的有效性，且實驗結果證明，本篇論文所提出的方法平均可達到94%以上的準確度。

With the ever-changing nature of techmology, internet of things (IoT) has become one of key applications of electronic systems. For IoT applications, such as object identification and internet of vehicle (IoV), image processing circuits are critical components. However, there might appear errors in this type of circuits due to aging or noises. This may make the generated images tend to be destroyed or even unable to recognize, leading to serious security concerns. The reliability of image processing circuits is thus of great importance.
In recent years, an innovative notion called error-tolerance has been proposed. The idea is that human beings might be imperceptible for some minor errors and thus this type of errors are acceptable. In this work, we apply this concept to image processing circuits. Only when the generated images are unacceptable, the target circuit needs to be repaired or reconfigured. Based on this concept, the maintainance cost of the circuits can be reduced and their lifetime can also be extended effectively.
In this thesis we develop a no-reference error-tolerability test methodology. Image quality can be obtained by the proposed methodology without reference images. We only need the structure information of a target image such as edges. This is beneficial to facilitate development of an on-line error-tolerabiloty evaluation scheme. Not only the proposed methodology can be carried out in a real-time way, but also the required memory for storing the reference images can be eliminated. To verify the effectiveness of the proposed methodology, a total of 1,004,232 erroneous images with different error characteristics are employed. The experiment results show that a very high test accuracy (more than 94% on average) is achieved.

論文審定書 i
致謝 ii
摘要 iv
Abstract v
目錄 vi
圖目錄 viii
表目錄 x
第一章 概論 1
1.1 論文背景與研究動機 1
1.2 研究貢獻 2
1.3 論文章節概要 4
第二章 研究背景及相關文獻回顧 5
2.1 影像的容誤 5
2.2 錯誤率(Error-rate)與錯誤嚴重程度(Error-significance) 6
2.3 Application-level correctness 6
2.4 非關鍵點 (Non-critical spots) 7
2.5 FSIMc 8
2.6 影像容誤測試方法 10
2.7 影像錯誤特徵分析 13
第三章 應用於影像處理電路之無參考容誤測試方法 15
3.1 簡介 15
3.2 參考影像 17
3.3 邊緣偵測方法 19
3.4 測試影像之邊緣特性分析 (Edge Tendency Analysis) 23
3.4.1 邊緣比例 24
3.4.2 邊緣趨勢量化標準 25
3.5 假性邊緣偵測 (False Edge Detection) 29
3.6 臨界值決定方法 30
3.6.1 假性邊緣臨界值分析 31
3.6.2 動態臨界值偵測 34
3.7 極端值偵測 (Extreme-Value Checking) 38
第四章 錯誤影像產生方法與實驗結果分析 40
4.1 錯誤影像產生方法 40
4.1.1 JPEG2000影像壓縮標準 40
4.1.2 單一固接錯誤 (Single stuck-at fault) 41
4.1.3 反離散小波轉換電路(IDWT)模擬錯誤方法 42
4.1.4 編碼器(Encoder)模擬錯誤方法 42
4.1.5 錯誤影像分析 43
4.2 實驗結果 46
4.2.1 準確度分析 46
4.2.2 誤判影像類型分析 49
4.2.3 方法執行效能比較 51
第五章 硬體電路實現 54
5.1 硬體架構 54
4.2 假性邊緣偵測硬體電路內部架構 57
4.3 硬體效能 59
第六章 結論 61
第七章 未來展望 62
參考文獻 63

[1] J. Gubbi, R. Buyya, S. Marusic and M. Palaniswami, “Internet of things (IoT): A vision, architectural elements, and future directions,” Future Generation Computer Systems, 29(7): pp. 1645-1660, 2013.
[2] M. A. Breuer, S. K. Gupta and T. M. Mak, “Defect and error-tolerance in the presence of massive numbers of defects,” IEEE Design & Test of Computers, 21(3): pp. 216-227, 2004.
[3] Li, Xuanhua, and Donald Yeung. “Application-level correctness and its impact on fault tolerance.” Proc. IEEE 25th Int’l Symp. on High Performance Computer Architecture , pp. 181-192, 2007.
[4] Nowroth, Damian, Ilia Polian, and Bernd Becker. “A study of cognitive resilience in a JPEG compressor.” Proc. IEEE Dependable Systems and Networks With FTCS and DCC, pp. 32-41, 2008.
[5] H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Cheng and C.-W. Wu, "Low-cost error tolerance scheme for 3-D CMOS imagers," IEEE Trans. on Very Large Scale Integration (VLSI) System, 21(3): pp. 465-474, 2013.
[6] Y. Fang, H. Li and X. Li, "Lifetime enhancement techniques for PCM-based image buffer in multimedia applications," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 22(6): pp. 1450-1455, 2014.
[7] M. A. Breuer and, H. Zhu “An illustrated methodology for analysis of error tolerance,” Proc. IEEE Design & Test of Computers, 25(2): pp. 168-177, 2008.
[8] Li, Xuanhua, and Donald Yeung. "Application-level correctness and its impact on fault tolerance." Proc. IEEE 13th Int’l Symp. on High Performance Computer Architecure ,pp. 181-192, 2007.
 
[9] S. Shahidi and S. K. Gupta, “Estimating error rate during self-test via one’s counting,” Proc. Int’l. Test Conf., pp. 1-9, 2006.
[10] T.-Y. Hsieh, K.-J. Lee and M. A. Breuer, "An error rate based test method to support error-tolerance," IEEE Trans. on Reliability, 57(1): pp. 204-214, 2008.
[11] L.-T. Wang, C. E. Stroud, and N. A. Touba, System on Chip Test Architectures, Morgan Kaufmann, 2008.
[12] M. Shahid, A. Rossholm, B. Lovstrom, and H. J. Zepernick, “No-reference image and image quality assessment: a classification and review of recent approaches,” J. on Image and Image Processing, 40(1), 2014.
[13] L. Zhang, D. Zhang, X. Mou and D, Zhang, "FSIM: A feature similarity index for image quality assessment," IEEE Trans. on Image Processing, 20(8): pp.2378-2386, 2011.
[14] R. Maini and Himanshu Aggarwal, “Study and comparison of various image edge detection techniques,” Int’l. J. of Image Processing, 3(1): pp. 1-11, 2009.
[15] T.-Y. Hsieh, T.-A. Cheng and C.-R. Chen, "Error-tolerability evaluation and test for images in face detection applications," Proc. IEEE Asian Test Symp., pp. 1-6, 2017.
[16] W. K. Pratt, Digital Image Processing. 3rd ed., New York: Wiley-Interescience, 1976.
[17] J. Canny, “A computational approach to edge detection,” IEEE Trans. Pattern Analysis and Machine Intelligence, 8: pp. 639-643, 1986.
[18] D. Marr and E.C. Hildreth, “Theory of edge detection,” Royal Soc. London B, 207: pp. 187-217, 1980.
 
[19] Tong-Yu Hsieh and Chao-Ru Chen, “A No-Reference Error-Tolerability Test Methodology for Image Processing Applications,” IEEE Trans. Int’l Test Conf. in Asia, 2018.
[20] N. Ponomarenko, L. Jin, O. Ieremeiev, V. Lukin, K. Egiazarian, J.Astola, B. Vozel, K. Chehdi, M. Carli, F. Battisti and C.-C. Jay Kuo, “Image database TID2013:Peculiarities, results and perspectives,” Proc. Signal Processing: Image Communication, 30:pp. 57-77, 2015.
[21] S. Shahidi and S. K. Gupta, “A theory of Error-Rate Testing”, Proc. IEEE Int’l Conf. on Computer Design, pp. 438-225, 2006.
[22] Z. Pan and M. A. Breuer, ”Basing acceptable error-tolerant performance on significance-based error-rate (SBER),” Proc. IEEE VLSI test symposium, April 2008.
[23] N. Ponomarenko, V. Lukin , J. Astola and K. Egiazarian, “Analysis of HVS-Metrics’properties using color image database TID2013,” Proc. Advanced Concepts for IntelligentVision Systems, 9386: pp. 613-624, 2015.
[24] M.A. Breuer, “Intelligible test techniques to support error-tolerance,” Proc. IEEE Asian Test Symp., pp. 386-393, 2004.
[25] S. Shahidi and S. K. Gupta, “ERTG: A test generator for error rate testing,” Proc. IEEE Int’l Test Conf., pp. 1-10, 2007.
[26] W. K. Pratt, Digital Image Processing, 3rd ed., New York: Wiley-Interescience, 1976.
[27] J. Canny, “A computational approach to edge detection,” IEEE Trans. on Pattern Analysis and Machine Intelligence, 8: pp. 639-643, 1986.
[28] D. Marr and E.C. Hildreth, “Theory of edge detection,” Proc. Royal Soc. London B, 207: pp. 187-217, 1980.
[29] L. T. Wang, C. Stroud and N. Touba, System on chip test architectures, USA: Morgan Kaufmann, 2008.
[30] G. K. Wallace, “The JPEG Still Picture Compression Standards”, IEEE Trans. on Consumer Electronic, 38(1): pp. xviii – xxxiv, 1991.
[31] OpenJPEG library: an open source JPEG2000 codec,http://www.openjpeg.org/
[32] J.-R. Chen, Development of A Behavior-Level Error Simulation and Analysis Platform and Its Applications to Image Processing Circuits, Master's Thesis, Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, 2016.
[33] T.-Y. Hsieh and Y.-H. Peng, "Filtering-based error-tolerability evaluation of image processing circuits," Proc. IEEE Int'l. On-Line Testing Symp. , pp. 132-137, 2015.
[34] Y.-H. Peng, Development and Implementation of Efficient Test Methods for Image Processing Circuits, Master's Thesis, Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, 2015.
[35] T.-Y. Hsieh, Y.-H. Peng and K.-C. Cheng, "Structural variance based error-tolerability test method for image processing applications," IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 37(2): pp. 485-498, 2018.
[36] K.-C. Cheng, A Low-Cost Dependability Evaluation and Grading Method and Its Hardware Implementation for Image Processing Circuits, Master's Thesis, Department of Electrical Engineering, National Sun Yat-sen University, Kaohsiung, Taiwan, 2015.