隨著系統單晶片時代的來臨，要嵌入晶片中的模組數日益增加。每個模組彼此都有其資料相依性，需要透過系統的傳輸架構來彼此交換資料，所以在這些模組之間，資料的傳輸已經變成了增進系統效能的一個瓶頸。
本篇論文提出了一個匯流排架構合成的方法。當一個系統的軟硬分割和管線化排程完成後，我們利用這些資訊做進一步分析，以產生一個能夠符合系統流量限制的的匯流排架構。這個方法是從系統所需的最少系統匯流排(AHB)和一條周邊匯流排(APB)開始，以一次加入一條系統匯流排(AHB)的方式來產生匯流排架構。合成過程中我們會對整體架構做一些調整，例如將兩個硬體模組做合併，或是加入一些個別使用的區域匯流排等等。每次我們都能得到一個面積成本，而合成目標則是期望找到一個面積成本最小的匯流排架構。為了在龐大的設計空間內找出最佳解，我們使用了整數規劃(integer programming)的方法來產生匯流排架構。藉由本篇論文所提出的方法來自動產生匯流排架構，可以節省許多人工設計複雜系統匯流排架構的時間。

Modern system-on-chip consists of an increasing number of highly complex modules. The quality of the interfaces and throughput of communication connections between these components are crucial to the performance of the system, since communication is often the main bottleneck in modern application domains like multimedia.
In this thesis, a bus-based communication architecture synthesis approach is proposed. Given the result of hardware/software partitioning and pipelined scheduling, the proposed approach constructs a communication topology which meets the constraints. We begin with the minimum number of AHB and an APB, each time we add an AHB and do some transformation such as merging or setting local buses. Our goal is to find the bus architecture which has minimum area. We use integer programming to construct a bus architecture each time, until the bus architecture with the minimum area are found. By this approach, we can save a lot of time required to design the communication architecture manually.

CHAPTER 1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 RESEARCH CONTRIBUTION 2
1.3 ORGANIZATION 3
CHAPTER 2 BACKGROUND AND RELATED WORK 5
2.1 HW/SW PARTITIONING AND PIPELINED SCHEDULING 5
2.2 INTRODUCTION TO AMBA 6
2.3 INTRODUCTION TO CORECONNECT BUS ARCHITECTURE 11
2.4 WISHBONE FEATURES 15
2.5 INTEGER PROGRAMMING 17
2.6 PREVIOUS WORK 18
CHAPTER 3 COMMUNICATION ARCHITECTURE SYNTHESIS 22
3.1 SYNTHESIS FLOW 22
3.2 PRE-PROCESSING 24
3.2.1 Input Specification 24
3.2.2 IP Classification 25
3.2.3 Communication Conflict Graph 27
3.2.4 Merging Hardware IPs 28
3.2.5 Setting Local Bus 30
3.3 BUS SYNTHESIS 31
3.3.1 Decision Variables 32
3.3.2 Constraints 33
3.3.3 Objective Function 39
CHAPTER 4 EXPERIMENTS AND RESULTS 43
4.1 MP3 DECODER 44
4.2 JPEG ENCODER 46
4.3 SYNTHETIC CASE 48
CHAPTER 5 CONCLUSION 52
References ……………………………..……………………………………………………54

[1] C.-T. Hsieh and M. Pedram, “Architectural Energy Optimization by Bus Splitting,” IEEE Transactions Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 4, pp. 408-414, April 2002.
[2] S. Pierre and A. Elgibaoui, “Improving Communication Network Topologies Using Tabu Search,” 22nd IEEE Conference on Local Computer Networks, pp. 44-53, November 1997.
[3] AMBA Specification (Rev 2.0). http://www.arm.com
[4] V. Raghunathan, M. B. Srivastava, and R. K. Gupta, “A Survey of Techniques for Energy Efficient On-Chip Communication,” Proceedings of the 40th Conference on Design Automation, pp. 900-905, June 2003.
[5] M. GASTEIER and M. GLESNER, “Bus-Based Communication Synthesis on System Level,” ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 1, pp. 1-11, January 1999.
[6] S. Pasricha, N. Dutt and M. Ben-Romdhane, “Rapid Exploration of Bus-based Communication Architectures at the CCATB Abstraction,” CECS Technical Report #04-11, May, 2004.
[7] J. Axelsson, “Architecture Synthesis and Partitioning of Real-Time Systems: A Comparison of Three Heuristic Search Strategies,” Proceedings of the Fifth International Workshop on Hardware/Software Codesign, pp. 161-165, March 1997.
[8] K. Lahiri, A. Raghunathan, and S. Dey, “Design Space Exploration for Optimizing On-Chip Communication Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, pp. 952-961, June 2004.
[9] B.-W. Kim, and C.-M. Kyung, “Exploiting Intellectual Properties With Imprecise Design Costs for System-on-Chip Synthesis,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 10, No. 3, pp. 240-252, June 2002.
[10] N. D. Liveris, and P. Banerjee, “Power Aware Interface Synthesis for Bus-based SoC Designs,” Proceedings of the Design, Automation and Test in Europe Conference and Exhibition Volume II, Vol. 02, No.2, pp. 864-869, 2004.
[11] Y. Cho, G. Lee, S. Yoo, K. Choi, and N.-E. Zergainoh, “Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design,” Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Vol.02, No.2, pp. 132-137, 2003.
[12] K. Anjo, A. Okamura, and M. Motomura, “Wrapper-Based Bus Implementation Techniques for Performance Improvement and Cost Reduction,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 5, pp. 804-817, May 2004.
[13] Y.-Y. Chen, Y.-C. Hsu, and C.-T. King, “MULTIPAR: Behavioral Partition for Synthesizing Application-Specific Multiprocessor Architectures,” European Conference on Design Automation, pp. 14-18, March 1992.
[14] C. H. Pyoun, C. H. Lin, H. S. Kim, J. W. Chong, “The Efficient Bus Arbitration Scheme in SoC Environment,” The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, pp. 311-315, July 2003.
[15] D. Li, Q. Yao, and P. Liu, “A Bus Arbitration Scheme for HDTV Decoder SoC,” Asia-Pacific Conference on Circuits and Systems, vol.2, pp. 79-83, October 2002.
[16] S. Pasricha, N. Dutt and M. Ben-Romdhane, “Automated Synthesis of Bus Architectures for Systems with Throughput Constraints,” CECS Technical Report #04-20, August 2004.
[17] Y.-C. Wu, Systematic Design and Implementation of SoC Interface IPs, Thesis for Master of Science, Department of Electrical Engineering, National Cheng Kung University, July 2004.
[18] S. H. Gerez, Algorithms for VLSI Design Automation, John Wiley & Sons Ltd, Baffins Lane, Chichester, West Sussex PO 19 1UD, England 1999.
[19] http://www.bayouworld.com/palmchip/pdf/coreframe01.pdf
[20] http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf
[21] http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf
[22] http://www-unix.mcs.anl.gov/otc/Guide/faq/nonlinear-programming-faq.html#Q1