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博碩士論文 etd-0801105-185200 詳細資訊
Title page for etd-0801105-185200
論文名稱
Title
應用整數線性規劃方法於軟硬體分割與管線化排程
HW/SW Partitioning and Pipelined Scheduling Using Integer Linear Programming
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
74
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2005-07-15
繳交日期
Date of Submission
2005-08-01
關鍵字
Keywords
整數線性規劃、管線化排程、軟硬體分割
pipelined scheduling, integer linear programming, HW/SW partitioning
統計
Statistics
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中文摘要
大部分多媒體嵌入式系統的設計目標,是以符合效能並且使用最低的成本為考量。在這篇論文中,我們提出二種整數線性規劃(Integer Linear Programming)為基礎的方法,來處理多媒體嵌入式系統的軟硬體分割(HardWare/SoftWare partitioning)和管線化排程(pipelined scheduling)問題。第一種ILP方法同時解決軟硬體分割和管線化排程。第二種ILP方法將軟硬體分割和管線化排程分割成兩個部份並且各別處理。第一個部份解決軟硬體分割和對應配置的問題,第二個部分則是解決管線化排程問題。我們所提出的兩種整數線性規劃的方法,不僅完成軟硬體分割,並且管線化排程這些計算工作,同時也考慮到通訊傳輸時間。我們所提出的第一種整數線性規劃方法的主要目標是在產能限制(throughput constraint)下,最小化計算工作元件的總成本,和管線化排程的級數(the number of pipeline stages)。我們所提出的第二種整數線性規劃方法的第一部分的主要目標是最小化計算工作元件的總成本;第二部份的主要目標是在產能限制之下,最小化管線化排程的級數。
最後,我們將所提出的整數線性規劃方法應用到三個實際多媒體應用的例子(JPEG Encoder, Wavelet Video Encoder, MP3 Decoder)以展示其效能。
Abstract
The primary design goal of many embedded systems for multimedia applications is usually meeting the performance requirement at a minimum cost. In this thesis, we proposed two different ILP based approaches for hardware/software (HW/SW) partitioning and pipelined scheduling of embedded systems for multimedia applications. One ILP approach solves the HW/SW partitioning and pipelined scheduling problem simultaneously. Another ILP approach separates the HW/SW partitioning and pipelined scheduling problem into two phases. The first phase is focusing on the HW/SW partitioning and mapping problem. Second phase is used to solve the pipelined scheduling problem. The two ILP approaches not only partition and map each computation task of a particular multimedia application onto a component of the heterogeneous multiprocessor architecture, but also schedules and pipelines the execution of these computation tasks while considering communication time. For the first ILP model, the objective is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint. In the second ILP approach, the objective of the first phase and second phase is to minimize the total component cost and the number of pipeline stages subject to the throughput constraint, respectively.
Finally, experiments on three real multimedia applications (JPEG Encoder, MP3 Decoder, Wavelet Video Encoder) are used to demonstrate the effectiveness of the proposed approaches.
目次 Table of Contents
PAGE
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 An Introduction To Integer Linear Programming 6
1.3 Research Contribution 8
1.4 Thesis Organization 8
CHAPTER 2 RELATED WORK 10
2.1 Related Survey 10
2.2 Problem Description 11
2.3 Design Flow 14
CHAPTER 3 PREPOSITIVE PROCESS 16
3.1 ASAP 16
3.2 ALAP 19
3.3 Input Specification 24
CHAPTER 4 ILP MODEL 26
4.1 Variables 26
4.1.1 Decision Variables 27
4.1.2 Estimation Variables 28
4.1.3 Result Variables 28
4.2 Combined ILP 29
4.2.1 Objective Function 29
4.2.2 Constraints 30
4.2.2.1 General Constraints 31
4.2.2.2 Resource constraints 31
4.2.2.3 Interface Constraints 31
4.2.2.4 Data Dependency Constraints 33
4.2.2.5 Pipelined Scheduling Constraints 33
4.2.2.6 Sharing Constraints 35
4.3 Example 36
4.4 Two-Phase ILP models 38
4.4.1 Phase-One ILP model 39
4.4.1.1 Objective Function 40
4.4.1.2 Constraints 40
4.4.1.2.1 General Constraints 40
4.4.1.2.2 Resource Constraint 41
4.4.1.2.3 Timing Constraints 41
4.4.2 Phase-Two ILP Model 42
4.4.2.1 Objective Function 42
4.4.2.2 Constraints 42
4.4.2.2.1 Data Dependency Constraints 43
4.4.2.2.2 Pipelined scheduling constraints 43
4.4.2.2.3 Sharing constraints 44
4.5 Constrains Complexity 44
CHAPTER 5 EXPERIMENTAL RESULTS 45
5.1 JPEG Encoder 45
5.2 MP3 Decoder 49
5.3 Wavelet Video Encoder 53
5.4 A Synthetic Example 57
CHAPTER 6 CONCLUSION AND FUTURE WORK 60
6.1 Conclusion 60
6.2 Future Work 61
Bibliography 62
參考文獻 References
[1] F. Balarin et al., Hardware-Software Co-Design of Embedded Systems: A Polis Approach. Norwell, MA: Kluwer, 1997.
[2] K. Chatha and R. Vemuri, "An iterative algorithm for hardware-software partitioning, hardware design space exploration and scheduling," Design Automation for Embedded Systems, Vol. 5, pp. 281-293, 2000.
[3] R. Niemann and P. Marwedel, "An algorithm for hardware/software partitioning using mixed integer linear programming," Design Automation for Embedded Systems, Vol. 2, pp. 165-193, March 1997.
[4] S. A. Khayam, S. A. Khan, and S. Sadiq, "A generic integer programming approach to hardware/software codesign," IEEE International Multi Topic Conference, pp. 6-9, Dec. 2001.
[5] P. Arat
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