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博碩士論文 etd-0801107-095753 詳細資訊
Title page for etd-0801107-095753
論文名稱
Title
奈米點非揮發性記憶體之電性分析與物理機制探討
Study on the Electrical Analysis and Physical Mechanism of Nanocrystal Nonvolatile Memory
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
77
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-20
繳交日期
Date of Submission
2007-08-01
關鍵字
Keywords
奈米點非揮發性記憶體
Nanocrystal Nonvolatile Memory
統計
Statistics
本論文已被瀏覽 5684 次,被下載 1797
The thesis/dissertation has been browsed 5684 times, has been downloaded 1797 times.
中文摘要
傳統的浮停閘快閃記憶體是利用連續的多晶矽半導體薄膜作為載子儲存的單元,而在元件尺寸持續微縮下此結構將面臨一些瓶頸,為了克服瓶頸因而衍生出兩種非揮發性記憶體結構:一種是SONOS非揮發性記憶體,另一種是奈米點 (量子點)非揮發性記憶體。
在本論文中,主要探討奈米點記憶體元件的電性分析,以物理能帶圖解釋所分析得到的記憶體相關現象。研究之奈米點記憶體元件有矽奈米點非揮發性記憶體及矽化鎳奈米點非揮發性記憶體。矽奈米點記憶體分為兩種結構,標準矽奈米點記憶體(穿隧氧化層/奈米點/控制氧化層 為 二氧化矽/矽奈米點/二氧化矽)及氮化過的矽奈米點記憶體(二氧化矽/矽奈米點/氮化矽薄膜/二氧化矽)。鎳奈米點記憶體分為兩種結構,標準矽化鎳奈米點記憶體(二氧化矽/矽化鎳奈米點/二氧化矽)及高介電常數矽化鎳奈米點記憶體(二氧化矽/矽化鎳奈米點/二氧化鉿)。
氮化矽層與矽奈米點的介面處會提供額外的缺陷以儲存電荷,有助於記憶體特性;而高介電常數材料成為控制氧化層,在相同電壓操作下,可使穿隧氧化層獲得較大的電場,以利於電荷的儲存及抑制閘極漏電。
Abstract
The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. The floating gate is a continuous semiconductor thin film which charges are stored in and able to move around. With the scaling of tunneling oxide, the thickness is decreased gradually. Once the tunneling oxide has been created a leaky path, all the stored charges in the FG will be lost after numerous counts of write/erase operation. When the tunnel oxide is thinner, the phenomenon happens more easily but the speed of write/erase operation is quicker. Therefore, there is a tradeoff between speed and reliability.Therefore, two approaches, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM.
In this thesis, the nonvolatile nanocrystal memory structures were proposed for electrical analysis and physical mechanism studied. We proposed two nanocrystal memory, silicon nanocrystal memory and nickel-silicide nanocrystal memory. The silicon nanocrystal memories have standard sample and nitridation sample. The interface between the nitride and Si-dots can offer extra trap cites for electrons storage. And the nickel-silicide dots memory has standard sample and high-k sample. The HfO2 layer for control oxide can increase the electric field of the tunnel oxide to get better programming efficiency.
目次 Table of Contents
Abstract (Chinese) ……………………………………………………. i
Abstract (English) ……………………………………………………. ii
Acknowledgment (Chinese) …………………………………………. iv
Contents…………………………………………………………………v
Figure Captions……………………………………………………… viii

Chapter 1 Introduction………………………………………………….1
1.1 General Background…………………………………………... 1
1.2 Motivation……………………………………………………. 5
Figures……………………………………………………….. 6

Chapter 2 Basic Mechanisms of Nonvolatile Memories……………… 7
2.1 Introduction……………………………………………………. 7
2.2 Program/Erase Mechanisms……………………………………... 9
2.2.1 Fowler-Nordheim Tunneling Injection………………………... 11
2.2.2 Direct Tunneling Injection……………………………...….….. 12
2.2.3 Frenkel-Poole Tunneling Injection…………………………….. 13
2.3 Reliability of Nonvolatile Memories…………………………………. 13
2.3.1 Retention…………………………………………….… 13
2.3.2 Endurance……………………………………………... 14
2.4 Basic Physical Characteristic of Nanocrystals Memory………………14
2.4.1 Quantum Confinement Effect…………………………………. 14
2.4.2 Coulomb Blockade Effect……………………………...…15
Figures……………………………...……………………….. 16

Chapter 3 Characteristics of Silicon Nanocrystals Nonvolatile Memories with Different structures…………………… 22
3.1 Introduction…………………………………………………………… 22
3.2 Experimental Details………………………………………………….. 23
3.3 Results and Discussions………………………………………………. 23
3.3.1 C-V and I-V Characteristics…………………………………… 23
3.3.2 Program/Erase Characteristics………………………………… 26
3.3.3 Retention Characteristics…………………………………….... 28
3.4 Summary…………………………………………………………….... 28
Figures……………………………………………………..……..….... 29

Chapter 4 Characteristics of Nickel-Silicide Nanocrystals Nonvolatile Memories with Different structures…………………… 42
4.1 Introduction……………………………………………………..…...... 42
4.2 Experimental Details……………………………………..…................ 43
4.3 Results and Discussions……………………………………..…........... 45
4.3.1 C-V and I-V Characteristics for the standard and high-k memory devices…………………………………………..….................. 45
4.3.2 The difference between C-V and pulse (P/E) operation............. 46
4.4 Summary……………………..….......................................................... 47
Figures……………………..……………………………………......... 48

Chapter 5 Non-ideal memory appearances................................................. 55
5.1 Introduction........................................................................................... 55
5.2 Experimental Details............................................................................. 55
5.3 Results and Discussions........................................................................ 56
5.4 Summary............................................................................................... 57
Figures.................................................................................................. 57


Chapter 6 Conclusion……………………..….....................................................60
6.1 Conclusion……………………..…....................................................... 60

References
參考文獻 References
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Chapter 2
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Chapter 3
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Chapter 4
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