本論文提出一種具有容錯(fault tolerant)與無死結(deadlock-free)特性之客製化三維網路晶片(3D NoC)合成方法。本研究中，在系統層級平面規劃下考慮容錯(fault tolerant)的功能，並且同時模擬合成處理元件(Processing Element, PE)和通訊元件的結構，我們稱它為3D-NoC-FT。實驗結果說明，3D-NoC-FT比起先前研究客製化的三維網路晶片(3D NoC)有更低的功率消耗。而且3D-NoC-FT也更具可擴展性，這使得它非常適合用在複雜的三維網路晶片(3D NoC)設計上。實驗結果顯示，比起先前無考慮連線(link)容錯的三維網路晶片(3D NoC) 之研究3D-SAL-FP，本論文所採用的3D-NoC-FT方法節省了1.67X的功率消耗，但亦付出相對性的代價：增加17%的時間延遲與產生35%的矽穿孔(TSV)個數。

This thesis proposes a synthesis methodology which is capable of fault-tolerance and deadlock-free for constructing a custom NoC topology in 3D ICs. In this thesis, the processors and their communications can be synthesized simultaneously in the system-level floorplanning with fault tolerant consideration, called 3D-NoC-FT. Experimental results show that the pro-posed 3D-NoC-FT produces custom 3D NoCs with lower power dissipation than previous works. This method is also more scalable, which makes it ideal for complicated 3D NoC de-signs. Compared with the previous 3D NoC work (3D-SAL-FP) without link fault tolerance, our fault tolerant method outperforms on the average the power dissipation by 1.67X with rela-tively small overhead of latency by 17% and the number of TSV by 35%, respectively.

CHAPTER 1 簡介 1
1.1 背景 1
1.2 研究動機 5
1.3 貢獻 5
1.4 論文架構 5
CHAPTER 2 相關文獻探討 6
CHAPTER 3 問題描述 9
3.1 問題描述 9
3.2 符號與定義 11
CHAPTER 4 拓樸產生演算法- 3D-NOC-FT 13
4.1 PHASE I: TRANSFORMATION FROM 2D TO 3D 13
4.2 PHASE II: TOPOLOGY CONSTRUCTION 20
4.3 PHASE III: DEADLOCK RECOVERY FOR ENSURING DEADLOCK FREE CHARACTERISTICS 23
4.4 PHASE IV: WIRELENGTH-AWARE FLOORPLANNING 24
CHAPTER 5 實驗結果 25
5.1 實驗環境與設定 25
5.2 實驗結果 25
5.2.1 和2D Mesh比較 (Table 5 2) 25
5.2.2 和3D ASIC NoC比較 (Table 5 4、Table 5 5) 27
5.2.3 和2D ASIC NoC比較 (Table 5 6) 28
5.2.4 相同的製程參數下比較3D-NoC-FT和3D-SAL-FP (Table 5 4) 28
5.2.5 相同的製程參數下比較3D-NoC和3D-SAL-FP (Table 5 5) 29
5.2.6 #Tier=1的3D-NoC-FT和3D-NoC與CosiNoC比較 (Table 5 9、Table 5 10) 30
5.2.7 層數不同的比較 (Table 5 7、Figure 5 1) 31
CHAPTER 6 結論 39
參考文獻 40
PUBLICATION LIST 46

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