由於現今無線通訊系統對於高傳輸速率之需求，促使IEEE 802.11a協定成為近年發展之主流，其傳輸速率可高達54 Mbps。為了達到如此高的資料傳輸率，符合該協定之通訊元件須同時具備高轉換增益及高線性度之特性，其中線性度又常以三階截斷點表示之。傳統的上變頻與下變頻混頻器僅分別具有0 dBm及 -5 dBm之三階截斷點，該線性度已明顯不足以滿足IEEE 802.11a傳輸速率之需求。因此，本論文運用TSMC 0.18 μm製程開發應用於IEEE 802.11a協定之高線性度混頻器設計。
本論文所設計之上變頻混頻器可應用於5-6 GHz之頻帶，符合IEEE 802.11a應用之頻率範圍，晶片尺寸為1.01 mm × 0.85 mm。為了有效提高該元件之線性度及頻寬，且不犧牲轉換增益，整個電路架構包含一個具gm-boosted結構之轉導級電路、具接地LO-body端設計之開關級電路，以及具shunt-peaking結構之負載級電路。經由量測結果顯示，該上變頻混頻器在5.2 GHz、5.4 GHz與5.8 GHz的頻率下，分別具有7.1 dB、7.2 dB與6.3 dB之高轉換增益，以及8.9 dBm、9 dBm與 13.2 dBm之高三階截斷點；同時在1.2 V之供應電壓下，其DC消耗功率為6.86 mW。
另一方面，本論文所設計之下變頻混頻器應用於5.2 GHz之頻率，晶片尺寸為1.02 mm × 0.86 mm。為了有效提高該元件之線性度與隔離度，以及抑制高階雜訊，整個電路架構包含一個具Dual-Gate結構之轉導級電路以及具RC-Tank結構之負載級電路。經由電磁模擬分析，該下變頻混頻器具有6 dB之轉換增益，以及0.8 dBm之高三階截斷點；同時在1.8 V之供應電壓下，其DC消耗功率為6.75 mW。

The IEEE 802.11a has become the mainstream protocol used in modern wireless communication system due to its high propagation rate of data (54 Mb/s). To meet high propagation rates, the communication devices used in IEEE 802.11a protocol usually present a high conversion gain and a high linearity (denoted as third order intercept point, IIP3). The IIP3 of conventional up- and down-conversion mixers are only about 0 dBm and -5 dBm, which fail to achieve a high propagation rate of data. This thesis utilizes the TSMC 0.18 μm CMOS technology to design and fabrication up- and down-conversion mixers with very high linearity for IEEE 802.11a application.
The proposed high-linearity up-conversion mixer with 1.01 mm × 0.85 mm chip size and its wide bandwidth (5~6 GHz) is well suited for IEEE 802.11a application. To enhance the linearity and bandwidth, a transconductor stage with gm-boosted structure, a switch stgae with LO-body grounded structure and a load stage with shunt peaking structure are adopted in this research. Under 5.2/5.4/5.8 GHz operating frequencies, the implemented up-conversion mixer demonstrates a high conversion gain of 6.8/7.1/6.3 dB and a high linearity of 8.9/9/13.2 dBm, respectivly. In addition, a moderate consuming power (6.86 mW) of such mixer can be achieved at 1.2 V supply voltage.
On the other hand, this thesis also designed and fabricated a high-linearity down-conversion mixer with chip size of 1.02 mm × 0.86 mm and 5.2 GHz center frequency. To improve the linearity and isolation and reduce the high-order noise, a transconductor stage with dual-gate structure and a load stage with RC-tank structure are adopted in this research. According to the EM-simulation resutls, the proposed down-conversion mixer presents a moderate conversion gain of 6 dB and a high linearity of 0.8 dBm. Additionly, a moderate consuming power (6.75 mW) of such mixer can be achieved at 1.8 V supply voltage.

摘要 i
Abstract ii
誌謝 iv
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究背景與動機 1
1.2 射頻接收機與發射機架構 3
1.2.1 收發機架構概述 3
1.2.2 外差式接收機架構簡介 4
1.2.3 直接降頻接收機架構簡介 5
1.2.4 直接升頻發射機架構簡介 6
1.2.5 二次升頻發射機架構簡介 7
1.2.6 總結 8
1.3 論文流程與概述 9
第二章 混頻器之原理概述 10
2.1 概述 10
2.2 混頻器之重要性能參數 13
2.2.1 轉換增益 13
2.2.2 線性度 14
2.2.3 雜訊指數 16
2.2.4 隔離度 25
2.3 混頻器之電路架構 26
2.3.1 被動式混頻器與主動式混頻器 26
2.3.2 單端輸出與差動輸出結構 27
2.3.3 單平衡式混頻器 29
2.3.4 雙平衡式混頻器 32
第三章 上/下變頻混頻器之設計 35
3.1 應用於IEEE 802.11a之高線性度下變頻混頻器 35
3.1.1 電路架構設計 35
3.1.2 模擬結果 40
3.1.3 實際電路佈局與考量 43
3.1.4 實際結果與討論 45
3.2 應用於IEEE 802.11a全頻帶之高線性度上變頻混頻器設計 47
3.2.1 電路架構設計 47
3.2.2 模擬與量測結果 54
3.2.3 實際電路佈局與考量 58
3.2.4 結果與討論 59
3.3 設計流程 60
3.4 量測考量 61
第四章 結論與未來展望 62
參考文獻 65

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