本論文提出符合IEEE 802.16e 標準的隨機解碼器。所提出的MEM（ Majority-based Edge Memories）架構的解碼器是MTFM（Majority-based Tracking Forecast Memories）機制的延伸，其錯誤修正的能力能比TFM架構的解碼器好，且在硬體面積上節省29%。本論文另外提供一個混合機制，混合MEM與傳統EM架構的隨機解碼器，此解碼器與純EM架構的隨機解碼器相比節省了約48%的硬體面積，且對錯誤修正的效能影響不大。此外在實現變數節點運算時，發現電路有能共用的子節點電路，在共用機制下，硬體面積額外節省了5%。最後本篇提出了一個新的提早結束機制，不僅能檢測檢查矩陣的偶同位關係否成立，並能同時偵測每個時間週期輸出的變數節點結果是否趨於穩定，基於這些終止條件，能大幅提升錯誤的控制能力。本論文所提出的硬體在90奈米合成下，所耗費的邏輯閘數量為401K，而工作時脈能達到525 MHz。

This thesis proposed an efficient design of stochastic low-density parity code （LDPC） decoder for IEEE 802.16e standard. Based on the proposed majority edge memory （MEM） architecture which is derived from the majority tracking forecast memory （MTFM） method, our design can perform better error correction capability and can save about 29% silicon area comparing to TFM-based design for irregular （576,288） IEEE 802.16 LDPC standard. Next, a hybrid design by mixing the use of MEM and traditional EM approaches is proposed, which can reduce more than 48% silicon area than the pure EM-based design for the implementation of IEEE 802.16 LDPC decoder. The bit-error-rate result is almost unaffected. Furthermore, we explore the sub-expression sharing technique in the implementation of variable nodes, which can save an additional 5% of area. Finally, a new termination scheme has also be proposed which will terminate the LDPC operations by not only detecting the satisfaction of parity check matrix, but also checking if the output of variable nodes can maintain steady for a certain number of the cycles. Based on these criteria, the error control capability can be increased a lot. The proposed LDPC decoder has been implemented with 90nm technology. The total number of gates is 401K, and can run up to 525MHz.

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖次 viii
表次 xiii
第一章 概論 1
1.1 研究背景與動機 1
1.2 論文大綱 2
第二章 隨機解碼與低密度同位檢查碼介紹 3
2.1 隨機計算簡介 3
2.1.1 隨機計算數值表示方式 3
2.1.2 隨機計算基本單元 4
2.2 低密度同位檢查碼（LDPC） 6
2.3 編碼方法 7
2.4 解碼演算法 9
2.4.1 Tanner Graph 9
2.4.2 SPA解碼演算法 10
2.5 以隨機計算實現和積演算法 14
2.5.1 隨機解碼-初始化 14
2.5.2 隨機解碼-檢查節點運算 15
2.5.3 隨機解碼-變數節點運算 16
2.5.4 隨機解碼-字碼的硬判定（Hard Decision） 18
2.6 變數節點隨機運算的栓鎖問題 19
2.6.1 雜訊相依性調整（Noise-Dependent Scaling，NDS） 20
2.6.2 邊緣記憶體（Edge Memory，EM） 22
2.6.3 循跡預測記憶體（Tracking Forecast Memory，TFM） 24
2.6.4 多輸入數變數節點的隨機運算 25
2.7 基於多數決機制的循跡預測記憶體（Majority-Based Tracking Forecast Memories，MTFM） 27
第三章 隨機解碼的分析與改進 32
3.1 持續狀態對於變數節點隨機運算的影響 32
3.2 EM、TFM與MTFM在隨機解碼器的效能分析 35
3.2.1 變數節點基於EM設計的隨機解碼器 36
3.2.2 變數節點基於TFM設計的隨機解碼器 38
3.2.3 變數節點基於MTFM基於的隨機解碼器 40
3.2.4 比較基於EM、TFM與MTFM設計的隨機解碼器 42
3.3 六輸入變數節點隨機運算架構的效能分析 43
3.4 硬判定機制（Hard Decision）對隨機解碼器的影響 45
第四章 IEEE 802.16e 隨機解碼器的硬體設計 47
4.1 變數節點基於MEM設計的隨機解碼器 47
4.1.1 基於MEM架構的變數節點介紹 47
4.1.2 基於MEM架構的六邊緣數變數節點之動作說明 49
4.2 混合型變數節點設計的隨機解碼器 52
4.3 變數節點的Shared IM機制 53
4.4 隨機解碼的提早結束機制（Early Termination，ET） 55
4.4.1 LDPC解碼器停止解碼運算的機制 56
4.4.2 LDPC隨機解碼具有穩定條件的提早結束判斷機制 57
第五章 隨機運算解碼器架構設計與實作 61
5.1 低密度同位檢查碼在IEEE802.16e標準之資訊 61
5.2 硬體架構與單元實作 64
5.2.1 通道機率隨機數產生器（Channel Probability Stochastic Number Generator，CPSNG） 67
5.2.2 亂數產生引擎（Random Number Engine，RNE） 67
5.2.3 檢查節點（Check Node，CN） 68
5.2.4 變數節點（Variable Node，VN） 68
5.2.5 字碼硬判定（Hard Decision） 72
5.2.6 提早結束機制電路（Early Termination，ET） 73
5.2.7 控制器（Controller） 74
5.3 隨機解碼器的硬體產生器 75
5.4 軟體驗證與FPGA驗證平台設置 77
5.4.1 軟體驗證 78
5.4.2 FPGA驗證 79
第六章 硬體效能與面積 83
6.1 隨機解碼器錯誤修正效能的比較 83
6.2 提早結束機制對於錯誤修正效能與解碼時間的影響 85
6.2.1 ET對於隨機解碼器錯誤修正效能的影響 85
6.2.2 ET對於隨機解碼器解碼時間的影響 87
6.3 變數節點記憶體需求的節省效果 89
6.3.1 變數節點中記憶體（EM）的需求 90
6.3.2 變數節點內部記憶體（IM）的需求 91
6.4 隨機解碼器硬體面積的比較 92
6.5 二進制與隨機運算解碼器的硬體面積比較 93
第七章 結論與未來展望 95
7.1 結論 95
7.2 未來展望 95
參考文獻 96

[1] D. J. C. Mackay and R. M. Neal, “Good codes based on very sparse matrices,” in Proc. 5th IAM conference on Computer Science. Springer Berlin Heidelberg, Dec. 1995, pp. 100-111.
[2] A. Alaghi and J. P. Hayes, “Survey of stochastic computing,” ACM Transactions on Embedded Computing Systems, vol. 12, no. 92, pp. 92：1-92：19, May. 2013.
[3] C. Winstead, V.C. Gaudet, A. Rapley, and C. Schlegel, “Stochastic iterative decoders,” in IEEE International Symposium on Information Theory, Sept. 2005, pp.1116-1120.
[4] A. Rapley, V. Gaudet, and C. Winstead, “On the simulation of stochastic iterative decoder architectures,” in IEEE Canadian Conference on Electrical and Computer Engineering, May. 2005, pp. 1868-1871.
[5] S.S. Tehrani, W.J. Gross, and S. Mannor, “Stochastic decoding of LDPC codes,” IEEE Communications Letters, vol. 10, no. 10, pp. 716-718, Oct. 2006.
[6] F.-P. Leduc, S. Hemati, W.J. Gross, and S. Mannor, “A relaxed half-stochastic iterative decoder for LDPC codes,” in IEEE Global Telecommunications Conference, Dec. 2009, pp. 1-6.
[7] S.S. Tehrani, A. Naderi, G.-A. Kamendje, G.-A. S.Hemati, S. Mannor, and W.J. Gross, “Majority-based tracking forecast memories for stochastic LDPC decoding,” IEEE Transactions on Signal Processing, vol. 58, no. 9, pp.4883-4896, Sept. 2010.
[8] A. Naderi, S. Mannor, M. Sawan, and W.J. Gross, “Delayed stochastic decoding of LDPC codes,” IEEE Transactions on Signal Processing, vol. 59, no. 11, pp. 5617-5626, Nov. 2011.

[9] M. Maamoun, R. Bradai, A. Naderi, R. Beguenance, and M. Sawan, “Controlled start-up stochastic decoding of LDPC codes,” in IEEE 11th International New Circuits and Systems Conference, June. 2013, pp. 1-4.
[10] S.S. Tehrani, A. Naderi, G.-A. Kamendje, S. Mannor, and W.J. Gross, “Tracking forecast memories in stochastic decoders,” in IEEE International Conference on Acoustics, Speech and Signal Processing, April. 2009, pp. 561-564.
[11] S.S. Tehrani, S. Mannor, and W.J. Gross, “Fully parallel stochastic LDPC decoders,” IEEE Transactions on Signal Processing, vol. 56, no. 11, pp. 5692-5703, Nov. 2008.
[12] E.R. William, “An introduction to LDPC codes,” Agust. 2003.
[13] The IEEE 802.16 Working Group Std. [Online]. Available： http：//www.ieee802.org/16/
[14] K.-L. Huang, V. Gaudet, and M. Salehi, “Out decisions for stochastic LDPC decoders,” in IEEE 48th Annual Conference on Inforamtion Sciences and Systems, March. 2014, pp. 19-21.
[15] MATLAB CENTRAL, LDPC codes BER simulation [Online]. Available： http：//www.mathworks.com/matlabcentral/fileexchange/14869-ldpc-codes-ber-simulation
[16] S.S. Tehrani, S. Mannor, and W.J Gross, “An area-efficient FPGA-based architecture for fully-parallel stochastic LDPC decoding,” in IEEE Workshop on Signal Processing Systems, Oct. 2007, pp.255-260.
[17] Xillinx Coporation, Virtex-5 User Guide [Online]. Available： http：//www.xilinx.com/support/documentation/user_guides/ug190
[18] J.-H. Huang and S.-G. Chen, “A 1.45Gbs （576,288） LDPC decoder for 802.16e standard”, in IEEE International Symposium Conference on Signal Processing and Information Technology, Dec. 2007, pp.916-921.
[19] T.-C. Ou, Z. Zhang, and M.C. Papefthymiou, “An 821MHz 7.9Gb/s 7.3pJ/b/iteration charge-recovery LDPC decoder,” in IEEE International Solid-State Circuits Conference on Digest of Technical Papers, Feb. 2014, pp.462-463.