隨著半導體製程的進步，電子元件尺寸可有效縮小。然而晶片也因此更容易受到製造缺陷(defect)或製程參數飄移的影響。如何有效提升晶片良率一直以來為學術界及工業界的重點研究項目之一。另一方面，對於醫療、汽車、飛機、處理器等應用來說，穩定度相當重要，錯誤存在時所需付出的代價可能極高。傳統上可透過容錯技術將錯誤效應進行遮罩或修正，但所需成本可能相當可觀。效能下降容忍是近幾年來被提出可有效率提升電路良率及穩定度之嶄新觀念。此觀念之基礎在於電路中可能存在一特殊種類的錯誤，稱之為效能下降錯誤。當系統內存在此種錯誤時系統功能不會產生任何錯誤結果，僅會使系統效能下降。倘若下降之幅度對市場應用來說仍可接受，則此晶片極有可能仍可繼續使用。效能下降容忍技術聚焦在分析待測電路內效能下降錯誤所導致之效能下降幅度，並根據分析結果將待測電路進行適當分類，將不同效能等級的電路應用於適當的電子產品中，藉此提升電路的有效良率及利潤。針對電路中存在效能下降錯誤將導致嚴重系統效能下降的元件，我們則可使用容錯設計加以保護，使系統效能仍在可接受範圍內。由於這些關鍵元件通常僅占整體面積之一小部分，透過僅保護這些元件，所需之硬體成本將可有效降低。
本論文提出一效能下降容忍應用方法，並使用可用來提升處理器運算效能之數值預測器作為案例探討。此方法提供一流程讓使用者可一步步將效能下降容忍應用在適當電路。針對數值預測器中佔有絕大面積之記憶體，我們注入不同錯誤密度的多重stuck-at faults並分析其效能下降程度。利用CPU95 與 CPU2006標準測試程式所進行的實驗結果顯示，數值預測器中所有的錯誤均為效能下降錯誤。當錯誤密度為1%時，幾乎不會導致任何效能下降，而即使錯誤密度高達20%，效能下降也僅有10.95%。針對存在錯誤時將導致18.51%至22.13%效能下降的關鍵邏輯元件(面積僅佔整體電路的0.046%)，我們使用常用之三模冗餘技術加以保護，而所需額外付出之面積成本僅有0.13%。

The advance in semiconductor manufacturing processes leads to feature size shrink of transistors. However, chips thus become more sensitive to process defects and variation. How to effectively improve yield has been one of the hot research topics in both the academia and the industry. On the other hand, for some critical applications such as medical systems, vehicle and aircraft systems or processors, reliability is of great importance. Conventionally by using some fault tolerance techniques, fault effects can be masked or corrected. Nevertheless, the required cost may not be affordable. Performance degradation tolerance (PDT) is a new notion that has been proposed recently to efficiently enhance effective yield and reliability of designs. This notion concentrates on one special type of fault, called performance degrading fault (pdef). This type of faults can only result in some performance degradation without any computation errors. If the degree of the degraded performance is still acceptable for marketing, the chips containing pdef are quite likely to be still marketable. The main focus of PDT is to carefully analyze the induced performance degradation by pdef, and properly grade target chips according to the analysis results. By selling the graded chips to different applications, the effective yield and profit of target products can be enhanced. For the critical components of a target design where pdef would induce significant performance degradation, fault tolerance techniques can be used to protect these components such that the degraded performance is still acceptable. Since such components usually occupy only a small area of the whole design, by only protecting only these components, the required hardware cost can be effectively reduced.
In this thesis we propose a PDT application methodology, and employ a value prediction unit that can enhance the performance of processors as a case study. This methodology provides a step-by-step guideline for the users to apply PDT to adequate applications. Targeting the memories that occupy the most area of a value predictor, we inject multiple stuck-at faults with various fault densities to analyze the induced performance degradation. The experimental results based on CPU95 and CPU2006 benchmark programs show that all faults in a value prediction unit are all pdef. When the fault density is 1%, almost no degradation is induced. Even when the fault density is 20%, the degradation is only 10.95%. For the critical logic part where pdef would induce 18.51%~22.13% degradation, the common triple modular redundancy (TMR) method is used to protect this part. The required hardware overhead is only 0.13%.

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖次 vi
表次 ix
第一章 介紹 1
1.1 研究動機 1
1.2 貢獻 5
1.3 章節介紹 6
第二章 背景知識與過去相關研究 8
2.1 容錯 8
2.2 效能下降錯誤 8
2.3資料相依性 10
2.4數值預測及數值預測器背景介紹 12
2.5效能下降之分支預測器 16
2.6效能下降之快取記憶體 17
第三章 支援效能下降容忍流程 19
第四章 數值預測器效能下降容忍度分析 22
4.1 目標電路 - 混合型數值預測器 22
4.1.1二階步階數值預測器 23
4.1.2限定內容方法數值預測器 27
4.1.3 數值標籤預測器 31
4.1.4 混合型預測器選擇機制 34
4.2數值預測器組態 36
4.3實作結果 38
4.4分析環境 39
4.5效能評估 - 預測準確度與覆蓋率 41
4.6效能分析 42
4.7錯誤分析 45
4.7.1二階步階數值預測器分析結果 46
4.7.2限定內容方法數值預測器分析結果 49
4.7.3數值標籤預測器分析結果 52
4.7.4預測器選擇機制分析結果 61
4.8重新設計 62
4.9 有效良率提升評估 64
第五章 結論 66
參考文獻 67

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