隨著積體電路的進步，良率與可靠度已成為十分熱門且重要的議題之一。容誤為最近幾年所提出可用來提升晶片有效良率及穩定度之嶄新觀念。此觀念的相關研究尚在萌芽階段，仍須深度探討。本論文旨在對JPEG2000編碼器與解碼器進行容誤(Error-Tolerance)分析與設計。JPEG2000相較於JPEG有更高的壓縮率，在相同的壓縮率下也有較好的影像品質。針對JPEG2000編解碼器中之離散小波轉換及量化器，我們發現這些元件相當適合用來進行容誤研究，因此在此論文中我們將這些元件實現出來，並注入錯誤進行錯誤分析。我們針對電路有錯誤時所得之圖片進行品質分析，並以PSNR(Peak Signal-to-Noise Ratio)與SSIM (Structural SIMilarity)作為影像品質評估指標。分析結果顯示，在圖片品質仍可接受下，離散小波轉換電路中最多有76.7%的錯誤可接受，反離散小波轉換電路最多有78.6%的錯誤可接受，而量化器中最多有68.4%的錯誤可接受。更且，這些分析結果除了展示了這些元件的錯誤容忍度外，也顯示了我們可針對電路含有可接受錯誤之部分進行簡化以降低面積、運算時間及功率消耗之優點。此優點也有助於提升晶片之良率。藉由將電路以此方式進行重新設計，我們發現在輸出圖片品質仍可接受的條件下，離散小波轉換電路的面積最多可減少63.3%、運算時間最多可減少24.7%、功率最多可降低54.6%，而產生之影像品質PSNR範圍為26.28 dB~39.91 dB，SSIM範圍為0.92~0.99。反離散小波轉換電路的面積則最多可減少63.4%、運算時間最多可減少27.4%、功率最多可降低53.2%，而量化器與反量化器所占的面積不到離散小波轉換的1%，其重新設計效益不大，因此不做重新設計，產生之影像品質PSNR範圍為25.42 dB ~40.81 dB，SSIM範圍為0.93~0.99。

With the advance of integrated circuits, yield and reliability have become one of the critical and popular issues to be addressed. Error-tolerance is a novel notion that can improve yield and reliability efficiently. The research of this notion is still in progress and needs further investigation to make this notion applicable in real applications. This thesis addresses error-tolerant analysis and design issues for JPEG2000 codec. JPEG2000 is a high performance image compression standard that can outperform JPEG with higher compression ratio under the same quality. Targeting the discrete wavelet transform (DWT), inverse discrete wavelet transform (IDWT) and quantization blocks of the JPEG2000 codec, we find that error-tolerance is quite adequate to be applied to these blocks. In this thesis we implement these components and inject faults to carry out fault analysis procedures. We carefully analyze the resulting image quality produced by the faulty components using the attributes of PSNR (Peak Signal-to-Noise Ratio) and SSIM (Structural SIMilarity). The analysis results show that under the constraint of acceptable image quality, there are up to {76.7%, 78.6%, 68.4%} acceptable faults in the implemented {DWT, IDWT, quantization} blocks. Furthermore, in addition to demonstrating the error-tolerability of these blocks, the analysis results also show that the sub-circuits that contain acceptable faults can be simplified so as to reduce the area, critical path delay and power consumption. This can also be helpful to increase chip yield. By properly simplifying the target blocks while still maintaining acceptable image quality, the {area, critical path delay, power consumption} of DWT and IDWT blocks are reduced by {63.3%, 24.7%, 54.6%} and {63.4%, 27.4%, 53.2%}, respectively. The resulting image quality of DWT (IDWT) is in the range of 26.28 dB~39.91 dB (25.42 dB~40.81 dB) in terms of PSNR and 0.92~0.99 (0.93~0.99) in terms of SSIM.

論文審定書 i
摘　要 ii
Abstract iii
目 錄 iv
圖 次 vi
表 次 ix
第一章 緒論 1
1.1 研究背景與動機 1
1.2 研究貢獻 2
1.3論文綱要 3
第二章 背景及相關文獻回顧 4
2.1容誤(Error Tolerance) 4
2.2 JPEG2000影像壓縮標準 5
2.3 一維離散小波轉換 7
2.3.1上提式(Lifting-Scheme)離散小波轉換 11
2.4二維離散小波轉換轉換 12
2.5 邊界效應處理(Boundary Treatment) 13
2.6.1 輸入零值延展 (Zero Padding) 14
2.6.2 相鄰數值延展 (Row Extension) 14
2.6.3 對稱延展 (Symmetric Extension) 15
2.6.4 嵌入式延展 (Embedded Extension) 16
第三章 架構及實現 17
3.1 二維DWT及IDWT硬體實現 17
3.2 離散小波轉換列處理器 (DWT Row Processor) 18
3.3 離散小波轉換行處理器 (DWT Column Processor) 22
3.4 逆向離散小波轉換行處理器與列處理器 (IDWT Column Processor & IDWT Row Processor) 29
3.5 量化器與反量化器 32
3.6 實作成果 34
第四章 錯誤分析 37
4.1 JPEG2000編解碼環境介紹 37
4.2 品質評估參數介紹 38
4.2.1 峰值信噪比 (Peak Signal Noise Ratio) 38
4.2.2 結構相似性 (Structural Similarity) 40
4.3 錯誤分析流程及方法 42
4.4 DWT錯誤分析 45
4.5 IDWT錯誤分析 61
4.6 量化器錯誤分析 76
第五章 重新設計方法及分析 77
5.1移除較低有效位元(Less Significant Bits Removing) 77
5.2 移除較高有效位元(More Significant Bits Removing) 81
5.3 移除多工器 87
5.4 混合重新設計方法討論 91
第六章 結論 104
參考文獻 105

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