本論文使用軟硬體共同設計的技巧設計一個MP3解碼系統，並且將這個系統實作在ARM Integrator快速驗證平台上。本系統主要的硬體架構是建立在LEON2 系統單晶片基礎架構，此架構包含一個相容於開放原始碼的SPARC-V8 CPU，還有AMBA規格的匯流排。由於MP3的解碼過程需要大量的計算，所以在這樣的一個基礎架構上，光是靠軟體是無法達到即時解碼的。因此我們利用一個本實驗室先前所發展且相容於AMBA 規格的逆改良式離散餘旋轉換(IMDCT)及多項合成濾波組 (poly phase synthesis filter bank) IP來加快系統速度。除了將LEON2處理器與逆改良式離散餘旋轉換及多項合成濾波組IP整合並且將MP3解碼程式中的浮點運算全部轉成定點運算，我們也配合ARM Integrator 平台新增或修改LEON2系統單晶片基礎架構 (例如新增FIFO、修改memory controller…等)，使得快速雛形驗證能夠順利進行。

In this thesis, a MP3 audio decoder has been designed as System-on-a-Chip using hardware/software co-design techniques. The MP3 audio decoder was built on a fast prototyping platform as ARM Integrator. The hardware architecture was built on the LEON2 SoC architecture, which contained an open source SPARC-V8 architecture compatible processor and an AMBA bus. Because MP3 decoding process was very computation-intensive for software-only decoder to decode in real-time on the LEON2 architecture, an IMDCT and poly phase synthesis filter bank hardware combined core pre-designed as an AMBA compatible core from our lab was reused and integrated. Besides integrating the IP, the MP3 decoding process was changed to use integer calculations instead of floating-point ones. In order to fast prototype LEON2 successfully on ARM Integrator, some modification of the LEON2 SoC hardware architecture was also made for example adding FIFO, modifying the memory controller, etc.

摘要
Abstract
List of Figures
List of Tables

Chapter 1 Introduction 1
1.1 Motivation 1
1.2 Overall approach 2
1.2.1 LEON2 2
1.2.2 ARM Integrator 3
1.2.3 Outline of the thesis 3
Chapter 2 MPEG Audio Layer III 4
2.1 Introduction to MP3 4
2.2 MP3 decoder theorem 6
2.2.1 Synchronization and CRC check 7
2.2.2 Side information 8
2.2.3 Scale factor selection information (SCFSI) 9
2.2.4 Side information format 10
2.2.5 Scalefactor decoder 10
2.2.6 Huffman decoder 12
2.2.7 Invert quantization 12
2.2.8 Reordering 13
2.2.9 Alias reduction 14
2.2.10 Stereo processing 14
2.2.11 IMDCT 15
2.2.12 Poly phase synthesis filter bank 17
Chapter 3 LEON2: A Soft Processor Core 19
3.1 Introduction 19
3.2 Compliance with SPARC 20
3.2.1 SPARC system components 21
3.2.2 SPARC instruction overview 24
3.3 Bus 24
3.3.1 AHB 25
3.3.2 APB 27
3.3.3 AMBA bus of LEON2 27
3.4 Memory 28
3.4.1 External memory access 28
3.4.2 Cache sub-system 29
3.5 Floating-point unit 30
3.6 Debug support unit 30
3.6.1 DSU 30
3.6.2 Trace buffer 32
3.7 Summary 33
Chapter 4 LEON2: Software Development Tools 37
4.1 LECCS 37
4.1.1 General development flow 38
4.1.2 RTEMS applications 38
4.1.3 Sequential C-programs 39
4.1.4 Memory organization 39
4.1.5 Making boot-proms 40
4.1.6 Running LEON2 programs from PROM 41
4.2 GRMON 42
4.2.2 Running applications in dsu mode 43
4.2.3 Running applications in simulator mode 43
4.3 RTEMS 44
4.4 SnapGear 46
Chapter 5 Development Platform 48
5.1 ARM Integrator 48
5.2 AP 48
5.3 CM 50
5.4 LM 51
Chapter 6 Implementation 53
6.1 MP3 system architecture 53
6.2 System architecture 54
6.3 LEON2 configuration 55
6.4 ZBT SSRAM 55
6.5 HIN232 57
6.6 FIFO 58
6.7 IMDCT and poly phase core design 59
6.8 Software enhancement 62
Chapter 7 Synthesis Result and Verification 66
7.1 System schedule 66
7.2 Synthesis result 68
7.3 Verification 71
7.4 ASIC error rate 71
Chapter 8 Conclusion 72

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