隨著半導體製程的改良，使得系統晶片日益複雜，在同樣面積上的系統晶片可以放入越來越多的元件之下，系統設計者已經開始尋找可以處理複雜系統並且可以快速模擬系統晶片運作的環境。目前文獻已經提出將設計的抽象層次提高至系統層級，亦即電子系統層級(Electronic System Level)的設計方法。然而，在目前的ESL設計環境之下，系統設計者仍然需要靠自己來決定系統的架構（各元件的連結方式），並且利用模擬的方式來分析軟硬體是否能夠達到需要的效能。然而，當系統非常複雜時，設計者要獲得最佳系統架構所要耗費的時間亦會隨著設計空間的變大而增加許多。
在本篇論文中，我們提出了一個電子系統層級自動化設計的方法，以輔助系統設計者在短時間內，從巨大的設計空間中決定系統的匯流排拓璞與記憶體配置。此方法主要是利用快速的評估方式，評估匯流排架構以及資料分配這些主要影響系統元件相互溝通的因素，在使用相同數目的運算元件下，進而獲得符合各項需求的系統架構。

Since semiconductor process is constantly being improved, the complexity of system-on-chip is rising daily and we can place more and more elements on the same chip area. The system designers have been searching new methodology that can handle the complex systems and the environment which can quickly simulate the system-on-chip. It is brought forward that is raising the level of abstraction, as the design methodology of Electronic-System-Level (ESL). But system designers still need to decide the system architecture (the bus and PE connection status), and judge if the system could meet the performance and cost constraints by simulation results. For the very complex system, system designers will cost more and more time owning to the growth of design space to get the best system architecture.
In this thesis, we propose a synthesis method to support automatic ESL design and help system designers to decide system architecture from large design space in short time. The method uses fast estimation method to estimate bus topology and memory allocation that affect the processing-elements’ communication. By this method, we can find better system architecture which meets all constraints with the same amount of processing-elements.

Chapter 1 Introduction 1
1-1 Motivation 1
1-2 Contribution 2
1-3 Organization 4
Chapter 2 Background and related work 5
2-1 Electronic System Level design 5
2-2 Genetic algorithm 11
2-3 Bus topology 17
2-4 Memory allocation 19
2-5 Related work 21
Chapter 3 System and algorithm description 25
3-1 Overview and system hypothesis 25
3-2 Proposed genetic algorithm 30
3-3 Heuristic performance estimation 32
3-4 Heuristic performance estimation with hybrid processing-elements type 38
Chapter 4 Experimental results 44
4-1 Before experimental results 44
4-2 MP3 system 45
4-3 Bus amount effect 46
4-4 ESL design and exploration 48
4-5 GA and exhaustive search 49
4-6 More cases 51
Chapter 5 Conclusion and future work 56
5-1 Conclusion 56
5-2 Future work 57

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