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博碩士論文 etd-0802115-181500 詳細資訊
Title page for etd-0802115-181500
論文名稱
Title
可高效率測試影像處理電路之方法開發與實現
Development and Implementation of Efficient Test Methods for Image Processing Circuits
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
97
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-07-28
繳交日期
Date of Submission
2015-09-02
關鍵字
Keywords
影像處理電路、錯誤發生率、容誤測試、良率、錯誤嚴重度、PSNR
error rate, image processing circuits, error significance, error-tolerability testing, PSNR, yield
統計
Statistics
本論文已被瀏覽 5673 次,被下載 23
The thesis/dissertation has been browsed 5673 times, has been downloaded 23 times.
中文摘要
隨著製程技術的進步,在一顆晶片上可以整合的電晶體數量越來越多,使得晶片越來越容易受到製程缺陷(Defect)的影響或是外界輻射、雜訊的干擾,導致晶片無法正常運作,良率與可靠率偏低。容誤為最近幾年提出可用來提升晶片有效良率與穩定度的新觀念。本論文針對影像處理電路(如JPEG2000解碼器)提出可支援容誤的測試方法,藉由仔細分析電路輸出影像的可接受度並區分出有錯可以接受的晶片,良率便可有效的提升。在容誤的測試方法中,需要解決的議題有兩個,包含影像的可接受度臨界值分析及晶片可接受度的測試。對於影像可接受度部分,我們仔細地分析錯誤影像,找出影像可接受的錯誤發生率與錯誤嚴重度臨界值,發現影像的可接受度會因為影像的大小、解析度、明亮度、對比度、頻率、及主觀感受的不同而有所差異。對於晶片可接受度的測試,在本論文中,我們提出兩個測試方法,第一個以影像品質評估參數PSNR為可接受度標準所推導的“等效錯誤發生率轉換”,透過驗證結果顯示,此測試方法與最詳盡的分析方法相比,均可有效地決定影像的可接受度,但節省的時間與儲存空間可達99%以上,且所需硬體成本僅有一般商用JPEG解碼器的1.36%。第二個則是考量人類感官對於不同錯誤具有不同敏感度的特性,由於我們對於影像的結構資訊較為敏感,因此這個方法中透過計算影像結構資訊,決定錯誤影像的可接受度,再進一步地評估待測電路的可接受度,且此測試方法與具有可評估影像結構資訊的SSIM參數相比,其準確度可達95.81%以上。在本論文的最後,我們結合了上述兩種測試方法,並實現了文獻中的向量壓縮方法硬體電路,提出了一個整合性的測試電路架構雛形,此整合性方法最高可更進一步提升4%以上的可接受度判斷準確度。
Abstract
As the feature size of the semiconductor technology keeps scaling down, more and more transistors are integrated to a single chip. However, this also increases the susceptibility of chips to manufacturing defects as well as external disturbances/noises, which results in low yield and reliability of chips. In recent years error- tolerability has been proposed as a new way to design and test a reliable system. In this thesis, we focus on the application of error-tolerance to image processing circuits such as JPEG2000 decoder. By carefully analyzing the acceptability of the generated images to identify erroneous yet still acceptable chips, the effective yield can be improved. For error-tolerance, two key issues need to be addressed, namely acceptable threshold determination and acceptability evaluation. For the acceptable threshold determination issue, we first carefully investigate the acceptability threshold values of images in terms of error rate and error significance. The investigation results show that appropriate threshold values should be determined depending on a number of factors, including size, resolution, brightness, contrast and frequency of test images as well as human subjectiveness. For the acceptability evaluation, we propose two methods. The first method is called equivalent error rate transformation, which is based on the commonly used image quality evaluation parameter, PSNR. This method transforms all the error rates at various output bits of the circuit under test into an equivalent one at single one output bit to reduce test cost. The experimental results show that the proposed technique is as effective as the exhaustive test method. Moreover, our technique requires much less test time and storage space compared with the exhaustive test method. The achievable reduction ratio in test time and storage space is more than 99%. The other method addresses the issue that the attribute of PSNR does not consider human beings’ sensitivity to structural variances, which may result in misclassification of circuits under test. We thus propose a new attribute and the corresponding test flow. Compared with the more complicated attribute in the literature, called SSIM, which has been shown to be able to evaluate the acceptability of images accurately, our test method can achieve 95.81% accuracy. Finally we propose an integrated test method which combine the two test methods described above to carry out a more accurate test process. Data compression techniques are also discussed to reduce the incurred hardware cost. The experimental results show the test accuracy can be further increased by more than 4%.
目次 Table of Contents
論文審定書+i
摘要+ii
Abstract+iii
目錄+v
圖目錄+viii
表目錄+x

第一章 概論+1
1.1 論文背景與動機+1
1.2 研究貢獻+2
1.3 論文大綱+4
第二章 背景及相關文獻回顧+5
2.1 峰值信噪比 (Peak Signal Noise Ratio, PSNR)+5
2.2 結構相似性 (Structural Similarity, SSIM)+6
2.3 JPEG2000 8
第三章 基於等效錯誤發生率轉換的容誤測試方法+11
3.1 簡介+11
3.2 影像的可接受度分析+13
3.2.1 可接受的PSNR臨界值+13
3.2.2 可接受的錯誤發生率與錯誤嚴重度+18
3.3 高效率影像可接受度測試方法+21
3.3.1 單一錯誤的情況+21
3.3.2 多重錯誤的情況+21
3.3.3 等效錯誤轉換目標位元之決定+24
3.3.4 等效錯誤轉換之測試流程+27
3.4 錯誤發生率轉換之硬體實現+27
3.4.1 Equivalent # errors calculator+28
3.4.2 Equivalent error rate calculator+29
3.4.3 硬體實現結果+29
3.5 實驗結果+30
3.5.1 相鄰兩輸出位元的錯誤發生率等效關係+30
3.5.2 提出的錯誤發生率轉換方法之誤差+31
3.6 結果與討論+33
第四章 頻率導向的影像品質評估參數之電路測試方法+34
4.1 簡介+34
4.2 錯誤影像的結構錯誤類型+35
4.2.1 Blocking Effects+36
4.2.2 Blackening/Whitening Effects+37
4.3 頻率導向之影像可接受度評估方法+38
4.3.1 計算影像結構(頻率)資訊+39
4.3.2 FTLV數值之決定+41
4.3.3 影像可接受度評估的應用+46
4.3.4 影像可接受#PPR、#PB、#PW範圍之決定+51
4.3.5 不同FTLV數值與SSIM準確度分析+57
4.4 頻率導向的影像品質評估參數之硬體實現+62
4.4.1 硬體實現結果+63
4.5 結果與討論+63
第五章 等效錯誤轉換與頻率導向品質評估之整合型測試方法+64
5.1 簡介+64
5.2 測試向量壓縮+66
5.2.1 字典壓縮法+66
5.2.2 Bitmask 為基礎的字典壓縮法+67
5.3 Decompression硬體架構實現與結果+69
5.3.1 Prepare compressed data+70
5.3.2 Decoder+70
5.3.3 實作結果+71
5.4 整合型測試方法+72
5.4.1 電路架構說明+72
5.4.2 整合型測試方法的實驗結果+74
5.5 結果與討論+76
第六章 結論+78
第七章 未來展望+79
參考文獻+80
作者簡歷+83
參考文獻 References
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