在本篇論文中，我們提出一新穎元件為具中間隔離氧化層(Middle Partial Insulation, MPI)之垂直式電晶體(Vertical Middle Partial Insulation, VMPI)應用在無電容式單電晶體動態隨機存取記憶體(Capacitorless One Transistor Dynamic Random Access Memory, 1T-DRAM)，藉由TCAD的模擬輔助，我們比較VMPI元件與平面式中間隔離氧化層電晶體(Plane Middle Partial Insulation, PMPI)、傳統矽覆絕緣基板(Silicon on Insulate, SOI)元件等單體之性能，首先我們討論元件之基本電性，發現我們提出之VMPI元件較傳統SOI元件具有明顯的浮體效應(Floating body effect)，有助於提升1T-DRAM的可程式規劃視窗(Programming Window)，而在資料保存時間(Data Retention Time)的表現上，因為本體中性區的增加，加上中間隔離氧化層的輔助下，減少接面漏電流且降低電洞逸散機率，相較於傳統SOI元件皆有約5倍的效能提升；此外，因為VMPI元件為垂直式架構，除了增加本體中性區體積外，環繞式閘極(Gate-All-Around, GAA)結構對於資料的寫入能有更優秀的表現，這將對未來1T-DRAM提供一項極佳的解決方案。

In this thesis, we propose a novel vertical MOSFET device with middle partial insulator (MPI) or VMPI for capacitorless one transistor dynamic random access memory (1T-DRAM) application. In TCAD simulations, we compare the device performances of the planar MPI, conventional silicon-on-insulator SOI, and our proposed VMPI. Based on numerical simulation, we find out that the VMPI device has a large kink phenomenon for improving the programming window. As far as the data retention time is concerned, the hole carriers leaking into the source region are reduced due to the presence of a large pseudo neutral region and an effective blocking oxide layer. The retention time can thus be improved about 5 times when compared with conventional SOI counterpart. Furthermore, it should be noted that the gate-all-around (GAA) VMPI device structure not only increases the body pseudo-neutral region, but also enhances the 1T-DRAM performances, suggesting that the proposed VMPI can become a candidate for 1T-DRAM application.

第一章 導論 1
1.1 背景 1
1.2 論文回顧 4
1.3 動機 11
第二章 操作原理 12
2.1 運用機制 12
2.2 元件操作說明 13
第三章 元件製作 17
3.1 模擬元件 17
3.2 實作元件 19
第四章 研究方法與結果討論 21
4.1 研究方法 21
4.2 電性探討 23
4.2.1 元件架構說明 23
4.2.2 輸入與次臨界特性曲線 25
4.2.3 輸出特性曲線 28
4.3 1T-DRAM 應用探討 33
4.3.1 可程式規劃視窗 33
4.3.2 資料保存時間 43
4.3.3 元件容忍度 45
4.4 實作結果 48
第五章 結論與未來發展 52
5.1 結論 52
5.2 未來發展 52
參考文獻 53
個人著作 58
個人得獎相關文件 64

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