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論文名稱 Title |
具有源/汲極束縛點且自我對齊的新穎雙通道金氧半場效電晶體之短通道效應與射頻/類比性能特性探討 Investigation of Short-Channel Behaviors and RF/analog Performance in a Novel Self-Aligned Dual-Channel Source/Drain-Tied MOSFET |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
70 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2011-07-15 |
繳交日期 Date of Submission |
2011-08-03 |
關鍵字 Keywords |
射頻/類比、源/汲極束縛點、雙通道、自我對齊、超薄矽本體 source/drain-tied, RF/analog, extremely thin (ET) body, dual-channel, self-aligned |
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統計 Statistics |
本論文已被瀏覽 5723 次,被下載 0 次 The thesis/dissertation has been browsed 5723 times, has been downloaded 0 times. |
中文摘要 |
在本論文中,我們提出了一個具有源/汲極束縛點且自我對齊的超薄矽本體新穎雙通道金氧半場效電晶體(DC-SDT MOSFET),製程則是採用磊晶之矽鍺/矽來完成,所以我們並沒有使用昂貴的SOI基板,而是使用Bulk基板,這可以說是大大的降低製作成本,我們也同時研究了元件之直流特性以及在射頻/類比(RF/analog)上元件之基本性能,變化環境溫度對於元件操作性能上的影響也將一一被探討,並且與相似的架構來做比較,例如:本體束縛點(body-tied, DC-BT MOSFET)以及傳統之雙通道電晶體(DC-SOI MOSFET),根據ISE-TCAD 10.0之二維模擬結果,對於DC-BT MOSFET而言,我們提出之DC_SDT MOSFET改善之元件性能,例如: Ioff降低了47.6%,切換速度(switching speed)增強了18.1%,次臨界斜率(subthreshold swing)改善了13%,電壓增益增強了25%,而對於DC-SOI MOSFET而言,我們提出之DC-SDT MOSFET改善的元件性能包括: Ion增強了11.3%,晶格溫度在上通道與下通道分別降低了35.7%和35.5%,電壓增益增強了15%。而我們並不單單是與上述兩個元件做比較,也和現今之主流元件做了比較,例如: FinFET、Gate-all-around,經由比較後,我們確定我們提出之DC-SDT MOSFET不管是在電流驅動能力或是抑止短通道效應的能力上,都是較好的,所以對於微縮而言,DC-SDT MOSFET的確是個有潛力的元件。 |
Abstract |
In this thesis, a novel fully self-aligned bulk-Si device named dual-channel source/drain-tied (DC-SDT) MOSFET with extremely thin (ET) body is proposed. The process utilizes the multiple epitaxial growths of SiGe/Si layers, so the starting material is bulk-Si wafer instead of the SOI wafer. We have investigated the RF/analog performance, and the high temperature induced device stability degradation has also been also investigated. Moreover, we have compared this structure with the other similar transistors such as: body-tied MOSFET (DC-BT MOSFET) and conventional dual-channel MOSFET (DC-SOI MOSFET). Based on the simulation results, for the DC-BT MOSFET, our proposed DC-SDT MOSFET has improved the device performances such as: Ioff decreased 47.6%, switching speed increased 18.1%, S.S. improved 13%, and voltage gain increased 25%. Whereas for the DC-SOI MOSFET, our proposed DC-SDT MOSFET has also improved the device performances such as: Ion increased 11.3%, reduction of lattice temperature 35.7% and 35.5 in the top and bottom channels, voltage gain increased 15%. We not only compared with the above two similar transistors, but also compared to the other mainstream devices, such as: FinFET and Gate-all-around. After the comparisons, we confirm that the proposed DC-SDT MOSFET has better ON-state current and short-channel behaviors. For the scaling, DC-SDT MOSFET can truly become one of the strong candidates. |
目次 Table of Contents |
第一章 導論 1 1.1 背景 1 1.2 論文評述 2 1.3 動機 8 第二章 元件設計與模擬 10 2.1 元件的設計 10 2.2 元件模擬所用之物理模型說明 12 第三章 結果與討論 13 3.1 元件之直流特性比較 13 3.2 環境溫度對於元件性能之影響 27 3.3 元件之射頻/類比性能之比較 31 3.4 環境溫度對於射頻/類比性能之影響 37 3.5 DC-SDT MOSFET與參考文獻中元件特性之比較 40 第四章 結論與未來發展 43 4.1 結論 43 4.2 未來發展 44 參考文獻 45 個人著作 51 共同著作 53 個人得獎相關文件 58 |
參考文獻 References |
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