現今的半導體製程技術已正式跨進奈米領域，隨著尺寸不斷微縮，面積相同的晶片卻擁有更多的電晶體數量，進而提昇其工作頻率及性能。但微影技術已經接近瓶頸，所以我們必須另外尋找能夠提升電晶體效能的方法，應變矽就是目前的研究重心。在此論文裡，我們深入探討當N型與P型金氧半場效電晶體的通道受到應變時，其電性特性與可靠度分析。
為了讓通道產生應變，我們選擇利用外界機械應力來彎曲矽基板，此時通道將受到單軸張應力而產生應變。利用此方法，我們成功提高NMOS的汲極電流與載子遷移率，提升幅度分別為12％與6％。在PMOS方面，則無任何改變量。
另外，在可靠度分析方面，藉由1000秒的DC Stress，我們可以瞭解熱載子效應對應變矽的影響。在實驗結果中，NMOS與PMOS都得到同一個現象，就是當矽基板彎曲的曲率越大時，可靠度越差。

Semiconductor technology has already got into nanometer scale. As the dimension keeping scale down, we can get more transistor in the same area, and furthermore the frequency and performance are also enhanced. But nowadays the development of the lithography technology has come to the neck, we must find the other way to improve the performance of transistor. In this study, the strained silicon effect and reliability of CMOS are fully discussed.
In order to get strain from the channel, silicon substrate is bent by applying external mechanical stress, the lattice of channel will have strain due to uniaxial tensile stress. By this way, we successfully improve drain current and mobility of NMOS into 12% and 6%, respectively. But there is no variation for PMOS.
In addition, by DC stress, we can understand the hot carrier effect to strained silicon. In this work, both NMOS and PMOS present the same result, this is, as the silicon substrate is bent, the sharper of the curve, the worse of the reliability.

目錄.....................................................Ⅰ
圖目錄...................................................Ⅳ
表目錄...................................................Ⅸ
中文摘要.................................................Ⅹ
英文摘要.............................................. ⅩⅠ

第一章 緒論

1-1. 半導體元件的基礎結構...............................1
1-2. 研究動機...........................................3
1-3. 文獻回顧...........................................4
1-4. 本文結構...........................................7

第二章 理論基礎

2-1. 氮化矽應力層.......................................8
2-1-1. 氮化矽應力層形成原理..........................8
2-1-2. 氮化矽薄膜的量測方式.........................11
2-1-3. 張力應變對矽之電子特性的影響.................13
2-2. 金氧半場效電晶體..................................15
2-2-1. 概述.........................................15
2-2-1. 基本元件特性.................................17
2-2-3. 線性區與飽和區...............................19
2-3. 拉曼光譜分析......................................20
2-3-1. 概述.........................................20
2-3-2. 拉曼散射機制.................................21
2-3-3. 拉曼光譜的測定方法...........................23

第三章 實驗儀器與參數粹取

3-1. 實驗步驟..........................................24
3-1-1. 實驗前準備...................................24
3-1-2. Sample研磨...................................24
3-1-3. 量測設定.....................................25
3-2. 參數萃取..........................................27
3-3. 實驗儀器..........................................29
3-3-1. 研磨機台.....................................29
3-3-2. 量測機台.....................................30

第四章 結果與討論

4-1. 氮化矽薄膜對電性的影響............................32
4-2. 機械研磨的影響....................................37
4-3. 彎曲對電性的影響..................................38
4-4. 可靠度分析........................................48
4-5. 拉曼光譜分析結果..................................62
4-6. 低溫量測..........................................62

第五章 結論與未來展望

5-1. 結論..............................................67
5-2. 未來展望..........................................68

參考文獻.................................................70

表目錄
表4-1 有無氮化矽應力層對NMOS(W=10μm、L＝80nm)之參數比較表................................................34
表4-2 NMOS(W=10μm、L＝1μm)基板於彎曲前後之參數比較表....43
表4-3 NMOS(W=10μm、L＝0.1μm)基板於彎曲前後之參數比較表..43














圖目錄
圖1-1基礎元件結構........................................2
圖2-1當氮化矽沈積於矽基板上，不同的薄膜應力會對外觀造成影響.................................................10
圖2-2氮化矽應力層中矽與氮原子的個數比與殘留應力之關係...11
圖2-3 Si3N4作用於電晶體之示意圖...........................12
圖2-4 Intel於2004發表的應變矽結構.......................13
圖2-5（001）面上二重與四重簡併態的電子特性...............14
圖2-6積體電路的複雜性對年代演進之關係...................16
圖2-7積體電路的最小元件尺寸隨年代變化情形...............16
圖2-8 MOSFET透試圖......................................18
圖2-9 MOSFET操作方式及其輸出特性的I-V特性..............19
圖2-10拉曼散射的機制....................................22
圖3-1研磨機.............................................29
圖3-2量測平台...........................................30
圖3-3量測機台...........................................30
圖3-4溫控器與燈光控制機.................................31
圖4-1有無氮化矽應力層對NMOS（W=10μm、L＝1μm）之VD-ID曲線.................................................32
圖4-2有無氮化矽應力層對NMOS（W=10μm、L＝80nm）之VD-ID曲線.................................................33
圖4-3有無氮化矽應力層對NMOS（W=10μm、L＝80nm）之VG-gm曲線.................................................33
圖4-4有無氮化矽應力層對NMOS（W=10μm、L＝80nm）之飽和區VG-NID曲線...............................................34
圖4-5有無氮化矽應力層對PMOS（W=10μm、L＝1μm）之VD-ID曲線.................................................35
圖4-6有無氮化矽應力層對PMOS（W=10μm、L＝80nm）之VD-ID曲線.................................................36
圖4-7有無氮化矽應力層對PMOS（W=10μm、L＝80nm）之VG-gm曲線.................................................36
圖4-8 NMOS於研磨前後之比較..............................37
圖4-9 PMOS於研磨前後之比較..............................38
圖4-10不同曲率半徑之模具................................39
圖4-11基板彎曲(R=20mm)對NMOS（W＝10μm、L＝1μm）之VD-ID曲線................................................39
圖4-12基板彎曲(R=20mm)對NMOS（W＝10μm、L＝0.1μm）之VD-ID曲線..............................................40
圖4-13基板彎曲(R=20mm)對NMOS（W＝10μm、L＝1μm）之VG-gm曲線................................................41
圖4-14基板彎曲(R=20mm)對NMOS（W＝10μm、L＝0.1μm）之VG-gm曲線..............................................41
圖4-15基板彎曲(R=20mm)對NMOS（W＝10μm、L＝1μm）之飽和區VG-NID曲線.........................................42
圖4-16基板彎曲(R=20mm)對NMOS（W＝10μm、L＝0.1μm）之飽和區VG-NID曲線......................................42
圖4-17基板彎曲(R=20mm)對PMOS（W＝10μm、L＝1μm）之VD-ID曲線................................................44
圖4-18基板彎曲(R=20mm)對PMOS（W＝10μm、L＝0.1μm）之VD-ID曲線..............................................44
圖4-19基板彎曲(R=50mm)對NMOS（W＝10μm、L＝1μm）之VD-ID曲線................................................45
圖4-20基板彎曲(R=50mm)對NMOS（W＝10μm、L＝1μm）之VG-gm曲線................................................46
圖4-21基板彎曲(R=50mm)對NMOS（W＝10μm、L＝1μm）之飽和區VG-NID曲線.........................................46
圖4-22基板彎曲(R=50mm)對PMOS（W＝10μm、L＝1μm）之VD-ID曲線................................................47
圖4-23載子遷移率變化量與曲率半徑的關係..................47
圖4-24汲極電流變化量與曲率半徑的關係....................48
圖4-25 NMOS的熱載子效應.................................49
圖4-26 PMOS的熱載子效應.................................49
圖4-27 NMOS（W＝10μm、L＝1μm）於DC Stress 0s~1000s之線性區VG-NID曲線......................................50
圖4-28 NMOS（W＝10μm、L＝1μm）於DC Stress 0s~1000s之飽和區VG-NID曲線......................................50
圖4-29載子遷移率隨DC Stress時間變化曲線................51
圖4-30 NMOS基板黏於R＝20mm模具上之線性區VG-NID曲線.....52
圖4-31 NMOS基板黏於R＝20mm模具上之飽和區VG-NID曲線.....52
圖4-32 NMOS基板黏於R＝30mm模具上之線性區VG-NID曲線.....53
圖4-33 NMOS基板黏於R＝30mm模具上之飽和區VG-NID曲線.....53
圖4-34 NMOS基板黏於R＝40mm模具上之線性區VG-NID曲線.....54
圖4-35 NMOS基板黏於R＝40mm模具上之飽和區VG-NID曲線.....54
圖4-36 NMOS基板黏於R＝50mm模具上之線性區VG-NID曲線.....55
圖4-37 NMOS基板黏於R＝50mm模具上之飽和區VG-NID曲線.....55
圖4-38 PMOS（W＝10μm、L＝1μm）於DC Stress 0s~1000s之線性區VG-NID曲線......................................56
圖4-39 PMOS（W＝10μm、L＝1μm）於DC Stress 0s~1000s之飽和區VG-NID曲線......................................57
圖4-40 PMOS基板黏於R＝20mm模具上之線性區VG-NID曲線......57
圖4-41 PMOS基板黏於R＝20mm模具上之飽和區VG-NID曲線......58
圖4-42 PMOS基板黏於R＝30mm模具上之線性區VG-NID曲線......58
圖4-43 PMOS基板黏於R＝30mm模具上之飽和區VG-NID曲線......59
圖4-44 PMOS基板黏於R＝40mm模具上之線性區VG-NID曲線......59
圖4-45 PMOS基板黏於R＝40mm模具上之飽和區VG-NID曲線......60
圖4-46 PMOS基板黏於R＝50mm模具上之線性區VG-NID曲線......60
圖4-47 PMOS基板黏於R＝50mm模具上之飽和區VG-NID曲線......61
圖4-48拉曼光譜分析......................................61
圖4-49室溫與77K之VD-ID曲線比較圖........................63
圖4-50隨溫度變化之線性區VG-NID曲線.......................63
圖4-51隨溫度變化之飽和區VG-NID曲線.......................64
圖4-52 On-Off ratio與溫度關係圖..........................64
圖4-53隨溫度變化之VG-gm曲線.............................65
圖4-54載子遷移率與溫度關係圖............................65
圖4-55次臨界擺幅與溫度關係圖............................66

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