最近各種不同記憶體元件如靜態記憶體、動態記憶體、快閃記憶體、鐵電記憶體與磁性記憶體…等，已被廣泛地討論與應用。在揮發性與非揮發性記憶體中，未來在高密度非揮發性記憶體元件中的非破壞性讀取特性將是一項非常重要的特性。本研究將針對非揮發性鐵電記憶體元件中具有金屬-鐵電層-絕緣層-半導體層(MFIS)與金屬-鐵電層-金屬-絕緣層-半導體層(MFM)結構與特性進行討論。
在眾多鐵電材料中，應用於非揮發性鐵電記憶體元件的鈣鈦礦(ABO3)與鉍層鐵電(BLFS)結構的鐵電材料，也已被廣泛地討論。然而，由於PZT或是SBT鐵電材料具要較高的污染性，因此(Ba,Sr)TiO3 與Ba(Ti,Zr)O3鐵電薄膜被期待用來取代PZT或SBT作為鐵電材料之用。
根據系統面板化的觀念，對於非晶矽薄膜電晶體與多晶矽薄膜電晶體主動陣列顯示器之應用，其電晶體的切換特性也被廣泛地討論與研究。因此在未來發展中，將記憶體元件、控制元件、中央處理單元…等，電子元件整合在系統面板上將是一項重要的研究標的。從以上論點，本研究之目的擬將傳統非晶矽薄膜電晶體中的閘極氧化層替換為Ba(Zr0.1Ti0.9)O3 (BZT)成份的鐵電材料，以形成一電晶體與一電容器(1TC)結構的非揮發性鐵電記憶體元件。
在本論文中，首先在Pt/Ti/SiO2/Si 與 ITO玻璃基板上利用射頻磁控濺鍍法沉積BZT鐵電薄膜，並製作MFM與MFIS 結構。調整不同濺鍍參數如氧氣濃度、濺鍍功率、基板溫度、腔室壓力與沉積時間等製程參數，探討不同射頻磁控濺鍍法沉積參數對薄膜物性與電性的影響。
由XRD, AFM 及SEM分析，可以觀察到剛沉積的BZT薄膜之晶相、表面粗糙度、晶粒大小與薄膜厚度。另外從MFM與MFIS結構的C-V 與J-E 曲線中，也可以求得MFM與MFIS結構的最大電容值、介電常數值、記憶窗口與漏電流大小等。
另外經由在快速熱退火處理後，在Pt/Ti/SiO2/Si與ITO玻璃基板上，MFM結構的電容值、殘餘極化量與漏電流大小可以被改善。另外我們也發現使用退火後的BZT薄膜在BTV/BZT雙層結構上，也可以增加MFM結構的電容值、殘餘極化量與漏電流大小。
最後，本研究亦成功地研製出使用BZT作為閘極氧化層材料的1TC結構非揮發性鐵電記憶體元件同時也討論了；記憶體元件在線性區與飽和區的Ion/Ioff汲極電流比、汲極電流的記憶窗口、ID-VG、ID-VD曲線、臨界電壓與次臨界擺幅。從本論文的實驗結果發現，對於未來製作高儲存容量非揮發性鐵電記憶體元件在系統面板的應用上，於記憶元件中的閘極氧化層使用BZT鐵電薄膜將是一項不錯的選擇。

Recently, many kinds of memory devices had been discussed, such as static random access memory (SRAM), dynamic random access memory (DRAM), the flash memory, ferroelectric random access memory (FRAM), magnetron random access memory (MRAM) and etc. In the volatile and nonvolatile memories, the non-destructive readout feature of high density nonvolatile memories will play an important role in the future. The structure characteristics of nonvolatile FeRAM with non-destructive metal-ferroelectric-insulator-semiconductor (MFIS) and metal-ferroelectric-metal-insulator-semiconductor (MFM) structures would be discussed in this study.
Among many ferroelectric materials, such as pervoskite (ABO3) and bi-layer ferroelectric (BLFS) structures had been widely investigated and discussed for applications in non-volatile ferroelectric random access memory devices. However, the ferroelectric materials such as (Ba,Sr)TiO3 and Ba(Ti,Zr)O3 thin films were expected to substitute the PZT or SBT memory materials and improve the environmental pollution because of their lower pollution problem.
According to system on panel (SOP) concept, the switch characteristics of various thin-film transistors had been widely investigated for the amorphous silicon (a-Si) and poly-crystaline silicon (poly-Si) active matrix LCD (AM-LCD) display applications. Therefore, the integrated electronic devices such as memory device, control device, central processing unit (CPU) and etc will be important research and study in the future. According the statement, we would investigate that the ferroelectric Ba(Zr0.1Ti0.9)O3 (BZT) composition could be used in a one-transistor-capacitor (1TC) structure of the amorphous-Si TFT device to replace the gate oxide of random access memory devices.
In this study, the rf magnetron sputtering was used to deposit BZT ferroelectric thin films on Pt/Ti/SiO2/Si and ITO/glass substrates, and MFM and MFIS structures were also fabricated. The effects of various sputtering parameters on the physical and electrical characteristics of BZT thin films such as the oxygen concentrations, rf power, substrate temperature, chamber pressure and deposition time were discussed. From the XRD, AFM and SEM analysis, the various peaks, surface roughness, grain size and thickness of as-deposited BZT thin film were also found. From the C-V and J-E curves of MFM and MFIS structures, the maximum capacitance, dielectric constant, memory window and leakage current density were obtained.
After rapid thermal annealing (RTA), the capacitances, remanent polarization (P-E) curves and leakage current density of MFM structure in Pt/Ti/SiO2/Si and ITO/glass substrates were improved. In addition, we found that the higher capacitance, larger memory windows and lower leakage current density of BTV/BZT dual layer structure using annealed BZT films would be increased in this study.
Finally, the one-transistor-capacitor (1TC) structure of ferroelectric random access memory (FeRAM) with the gate oxide of BZT thin films on the amorphous silicon TFT structure have been fabricated and investigated. The Ion/Ioff drain current ratio, drain current window, ID-VG, ID-VD curves, threshold voltage (VT) and subthreshold swing (SS) properties of 1TC bottom-gated FeRAM device were obtained under the linear and saturation region.
From the results in this study, the BZT thin films for bottom-gated amorphous thin-film transistor will be a suitable candidate to fabricate with ferroelectric random access memory (FeRAM) devices for system on panel (SOP) applications.

第一章 緒論 1

1.1 簡介 1
1.1.1 非揮發性鐵電記憶體之應用 3
1.1.2 鐵電材料的種類 4
1.1.3 薄膜沉積方法 5
1.2 研究動機 5
1.3 本論文架構 6

第二章 理論分析 7

2.1 鈣鈦礦結構特性 7
2.1.1 鈦酸鋇鈣鈦礦結構特性 7
2.1.2 鋯元素摻雜對鈦酸鋇特性影響 8
2.2 (BLFS)結構特性 8
2.2.1 釩元素摻雜對鈦酸鉍特性影響 9
2.3 鐵電材料特性 9
2.3.1 介電極化和極化機構 9
2.3.2 鐵電性質 10
2.3.3 介電損失 11
2.3.4 漏電流 12
2.4 薄膜沉積原理 12
2.4.1 沉積現象 12
2.4.2 薄膜表面及截面結構 13
2.5 射頻磁控濺鍍原理 13
2.5.1 直流輝光放電 13
2.5.2 磁控濺射 14
2.5.3 射頻濺射 14
2.6 化學氣相沉積原理 15
2.7 真空蒸鍍系統原理 15
2.8 (MFM)與(MFIS)結構理論 16
2.8.1 鐵電記憶體的讀寫原理 16
2.9 薄膜電晶體理論 17
2.9.1 薄膜電晶體-液晶顯示器的原理 17
2.9.2 薄膜電晶體的理論 18
2.9.3 薄膜電晶體的臨界電壓 18
2.9.4 薄膜電晶體的次臨界區特性 19
2.9.5 薄膜電晶體的電子移動率 19

第三章 實驗步驟 20

3.1 鐵電薄膜沉積 20
3.1.1 基板的清洗步驟 20
3.1.1 ITO玻璃基板的清洗步驟 21
3.1.2 Ba (Zr0.1Ti0.9)O3濺鍍靶材的製作 21
3.1.2 (Bi4Ti3O12+V2O5)濺鍍靶材的製作 22
3.1.2 鈦(Ti)與白金(Pt)底電極基板製備 23
3.1.3 射頻磁控濺鍍系統與薄膜沉積 23
3.2 (MFM)與(MFIS)結構製作流程 23
3.3 快速熱退火處理………………………………….………24
3.4 非揮發性鐵電記憶體元件製作流程 24
3.4.1 非揮發性鐵電記憶體之光罩(Mask)製作 25
3.4.2 傳統式非揮發性鐵電記憶體元件製作 25
3.4.3 1TC Bottom-gated非揮發性鐵電記憶體結構 25
3.5 量測分析儀器 26
3.5.1 薄膜物性量測 26
3.5.1.1 掃描式電子顯微鏡 26
3.5.1.2 X光繞射儀 26
3.5.1.3 原子力顯微鏡 26
3.5.1.4 二次離子質譜儀 27
3.5.1.5 (α-step)薄膜厚度測量儀 27
3.5.2 薄膜電性量測……………………….…………………....27
3.5.2.1 介電常數量測 .27
3.5.2.2 漏電流特性量測 28
3.5.2.3 P-E曲線量測 28
3.5.2.4 記憶窗(Memory Window)量測 28
3.5.3 鐵電記憶體元件電流量………………………….……....29
3.5.3.1 臨界電壓參數萃取 29
3.5.3.2 臨界擺幅參數萃取 29
3.5.3.3 電子移動率參數萃取 29

第四章 結果與討論 30

4.1 非揮發性鐵電記憶體元件於矽基板特性 30
4.1.1 鐵電電容器結構 30
4.1.2 金屬-鐵電層-絕緣層-半導體電容器結構 36
4.1.3 BTV/BZT雙層結構特性探討 37
4.1.4 非揮發性鐵電記憶體元件製作與特性……………….38
4.2 非揮發性鐵電記憶體元件於玻璃基板特性 30
4.2.1 鐵電電容器結構 40
4.2.2 1TC-Bottom gated結構鐵電記憶體 46

第五章 結論 48
參考文獻 50

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