在本論文中，提出了一個高良率的新自我對齊製程來製作運用在1T-DRAM方面之具阻擋氧化層的金氧半，並且克服了舊製程[1]做法不易運用在薄埋氧化層元件上的問題。藉由TCAD 10.0的模擬，我們比較了傳統PDSOI的1T-DRAM架構及用此篇論文所提出的新作法所製作的具阻擋氧化層之部份空乏矽覆絕緣電晶體(bPDSOI)架構,我們發現在新架構Body兩旁的阻擋氧化層不僅能抑制短通道效應、降低Source/Drain與Body間P-N接面所造成漏電流與提高閘極對通道的控制能力，更能有效的降低1T-DRAM的功率消耗與提升整體上的操作速度。相較於傳統PDSOI DRAM，在同樣執行一Programming window為10 μA的讀寫動作中，新型1T-DRAM元件，bPDSOI在Wrtie “1”時所消耗的功率減少了39%，在Wrtie “0” 時所消耗的功率減少了25%，整體上的能量消耗僅為傳統PDSOI的23%且操作時間更短，Retention time更長。

In this paper, we propose a high-yield self-aligned process to form a silicon-on-insulator MOSFET with block oxide for 1T DRAM use. The new process can overcome the problem of the previous one [1], which cannot be used for a thin BOX devices. Based on the TCAD 10.0 simulation, we compared the conventional 1T-DRAM (PDSOI) with the partially depleted SOI with block oxide （bPDSOI） which used the new process presented in this thesis, We find that the device with block oxide embedded on body is not only obtain good short-channel effects immunity but also reduce leakage of the P-N junction between source/drain and the body and increase the gate controlability on the channel region. Moreover, it can decrease power consumption and raise the operation speed of the 1T-DRAM. Compare to the PDSOI DRAM to carry out 10 μA programming window, the power consumption of the new 1T-DRAM is diminished 39% of write “1” and 25% of write “0”. Furthermore, the energy consumption during memory operation is only 23% compared to that of the conventional PDSOI DRAM and it can short the operation time but achieve a long retention time.

第一章 導論 --------------------------------------------------------------------------- 1
第二章 阻擋氧化層之新自我對齊製程設計 ------------------------------------ 10
2-1 理想模擬製程 --------------------------------------------------------- 10
2-2 實際製作製程 --------------------------------------------------------- 12
第三章 結果與討論 ------------------------------------------------------------------ 13
3-1 模擬結果 --------------------------------------------------------------- 13
3-1-0模擬所使用的物理Model說明 ------------------------------- 13
3-1-1 N-type bPDSOI特性探討 -------------------------------------- 15
3-1-2 N-type bPDSOI之1T-DRAM的應用 ------------------------ 24
3-2 N-type bPDSOI實作結果與討論 ----------------------------------- 39
第四章 結論 --------------------------------------------------------------------------- 45
第五章 未來發展 --------------------------------------------------------------------- 46
參考文獻 ------------------------------------------------------------------------------- 47
附錄A bPDSOI Runcard ------------------------------------------------------------ 51

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