Responsive image
博碩士論文 etd-0804110-170605 詳細資訊
Title page for etd-0804110-170605
論文名稱
Title
實作一個1.8V、12-位元、每秒100萬次取樣速率、管線式類比數位轉換器
Implementation of a 1.8V 12bits 100-MS/s Pipelined Analog-to-Digital Converter
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
94
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2010-07-28
繳交日期
Date of Submission
2010-08-04
關鍵字
Keywords
放大器、低功率、管線式、類比數位轉換器、比較器
Comparator, Amplifier, Low Power, Pipeline, ADC, Analog-to-Digital Converter
統計
Statistics
本論文已被瀏覽 5679 次,被下載 0
The thesis/dissertation has been browsed 5679 times, has been downloaded 0 times.
中文摘要
積體電路因為有著微小、省電及穩定度高等特性,故已廣泛的應用在日常生活中。“運算”是積體電路的主要功能之一,而目前積體電路的運算功能多以數位方式實現。數位電路雖然有眾多的優點,但受限於大自然的訊號都是類比的形式呈現,數位電路無法直接處理類比訊號,因此產生了類比數位轉換器的需求。
隨著積體電路製程進步,數位電路的處理速度加快,類比數位轉換器也被要求達到更高的轉換速度。除此之外,為了達到更高的畫質及更清楚的聲音,類比數位轉換器的解析度也需要向上提升;又如果加上可攜性產品的應用,也顯現出類比數位轉換器功率消耗大小的重要性,故學生以高速、高解析度且低電壓、低功率的概念,去設計實作類比數位轉換器。
本論文採用TSMC.18μm製程技術,分析管線式類比數位轉換器的架構,設計實作一個12位元,100萬取樣速率且低功率的類比數位轉換器。利用每階段1.5位元的架構,並使用動態比較器降低功率消耗,以及數位錯誤更正電路來取得最後的數位碼輸出。

關鍵詞:類比數位轉換器、管線式、低功率、放大器、比較器。
Abstract
Because IC (Integrated Circuit) has some good features like: little, low power consumption, and high stable, so it already popularly applied to our daily life. Operation is one of the main functions of IC, and now operate function achieve in digital mode of many IC products. Although digital circuits have many advantages, but we live in the analog world, natural signals are all analog. Digital circuits can’t direct process analog signals, and therefore we have a requirement of analog-to-digital converter.
As time goes by, IC technology has made great progress; digital circuits have faster process ability, and we also require a high speed analog-to-digital converter. Besides, in order to achieve higher picture quality and clearer voice, we also require a high resolution analog-to-digital converter. For portable products, the power consumption also needs to take into account. As mentioned above, I will implement a high speed, high resolution and low power analog-to-digital converter.
In this thesis, the circuits are designing with TSMC.18μm 1P6M CMOS process and 1.8V of supply voltage. The speed and resolution of ADC are 100Ms/s and 12bits individually. The pipelined coupling with 1.5bit/stage constitutes the main architecture of analog-to-digital converter. The dynamic comparator is used for lower power. Finally, the output codes are translated by digital correction circuit.

Keywords: ADC, Analog-to-Digital Converter, pipeline, low power, amplifier, comparator.
目次 Table of Contents
Chapter 1 Introduction 1
1.1. Motivation 1
1.2. Objective 2
1.3. Thesis Organization 3
Chapter 2 The principle of designing a pipeline ADC 4
2.1. Introduction 4
2.2. KT/C Noise 4
2.3. Switch 7
2.3.1. ON-Resistance 7
2.3.2. Charge Injection 7
2.3.3. Clock Feedthrough 8
2.4. Operational Amplifier 9
2.4.1. DC Gain 9
2.4.2. Bandwidth Requirement 11
2.4.3. A Example: Folded Cascode Amplifier 13
2.5. Comparator 15
2.5.1. Dynamic Comparator 17
2.6. Digital Correction Technique 18
2.6.1. 1.5 bit/stage 18
2.6.2. 2.8 bit/stage 19
2.7. Reference Voltage from Resistor 20
2.8. Sample And Hold Circuit 21
2.9. Power Consumption 22
Chapter 3 The implementation of ADC 23
3.1. Booster circuit 26
3.2. BIAS circuit 29
3.3. Switch 33
3.4. Amplifiers 36
3.5. SHA 42
3.6. MDAC 45
3.7. Dynamic Comparator 49
3.8. Clock generator 57
3.9. Two-bit flash ADC 59
3.10. Digital Correction circuit 61
Chapter 4 Simulation Result of ADC 62
Chapter 5 Measurement Result of ADC 68
5.1. Measurement consideration 68
5.2. measurement result and discuss 70
Chapter 6 Conclusion 75
Future improvement and research 76
References 77
參考文獻 References
[1]. J.Arias, V.Boccuzzi, L.Quintanilla, L.Enriquez, D.Bisbal, M.Banu, and J. Barbolla, “Low Pipeline ADC for Wireless LANs,” IEEE J.Solid-state circuits, vol. 39, pp. 1338-1340, August 2004.
[2]. M. Mohajerin, C. Chen and E. Abdel-Raheem, “A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends,” IEEE Pacific Rim Conference, pp.597 – 600, Aug. 2005.
[3]. B.K Ahuja, et al., “A 30 Msample/s 12b 110 mW video analog front end for digital camera,” IEEE International Conference of Solid-State Circuits, Vol.1, pp.438 – 479, Feb. 2002.
[4]. D. Kurose, et al., “55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers,” IEEE Journal of Solid-State Circuits, Vol.41, No.7, pp.1589 – 1595, July. 2006.
[5]. J. Francke, Y. Huazhong and L. Rong, “A 10-Bit, 40 MSamples/s Low Power Pipeline ADC for System-on-a-Chip Digital TV Application,” International Semiconductor Conference, Vol.2, pp.421 – 424, Sept. 2006.
[6]. Trojer, M.; Cleris, M.; Gaier, U.; Hebein, T.; Pridnig, P.; Kuttin, B.; Tschuden, B.; Krassnitzer, C.; Kuttin, C.; Pribyl, W., “A 1.2V 56mW 10 bit 165Ms/s pipeline-ADC for HD-video applications,” Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, pp.270 – 273, Sept. 2008.
[7]. B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Co.Inc, pp.420 – 421, pp.37 – 39, 2001.
[8]. O.A. Adeniran and A. Demosthenous, “Optimization of bit-per-stage for low-voltage low-power CMOS pipeline ADCs,” European Conference of Circuit Theory and Design, pp.55 – 58, Vol.2, Sept. 2005.
[9]. Y. Chouia, et al., “14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC,” Midwest Symposium of Circuits and Systems, Vol.1, pp.353 – 361, July. 2004.
[10]. C.J.B. Fayomi, G.W. Roberts, and M. Sawan, “Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization,” IEEE International Symposium of Circuits and Systems, Vol. 3, pp.2200 – 2203, May. 2005.
[11]. T.N. Andersen, et al., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18 μm Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol.40, No.7, pp.1506 – 1513, July. 2005.
[12]. R.J. BAKER, “CMOS CIRCUIT DESIGN, LAYOUT, AND SIMULATION, 2nd,” John Wiley, pp.132 – 135, pp.324, pp.727, pp.787, Oct. 2005.
[13]. S. Mallya and J.H. Nevin, “Design procedures for a fully differential folded-cascode CMOS operational amplifier,” IEEE Journal of Solid-State Circuits, Vol.24, No. 6, pp.1737 – 1740. Dec. 1989.
[14]. L. Sumanen, M. Waltari and K. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters,” IEEE International Conference of Electronics, Circuits and Systems, Vo.1, pp.32 – 35, Dec. 2000.
[15]. T.B. Cho and P.R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE Journal of Solid-State Circuits, Vol.30, No. 3, pp.166 – 172, March. 1995.
[16]. S.H. Lewis, et al., “A 10-b 20-Msamples analog-to-digital converter,” IEEE Journal of Solid-State Circuits,Vol.27, No.3, pp.351 – 358, March. 1992.
[17]. O.A. Adeniran and A. Demosthenous, “Optimization of Bit-per-Stage for Low-Voltage Low-Power CMOS Pipeline ADCs,” European Conference of Circuit Theory and Design, Vol.2, pp.55 – 58, Sept. 2005.
[18]. C.S.G. Conroy, D.W. Cline and P.R. Gray, “An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol.28, No.4, pp.447 – 454, April. 1993.
[19]. H. Charkhkar, A. Asadi, and R. Lotfi, “A 1.8V, 10-bit, 40MS/s MOSFET-only pipeline analog-to-digital converter,” IEEE International Symposium of Circuits and Systems, pp. 4, May. 2006.
[20]. J. Li and U.K. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique,” IEEE Journal of Solid-State Circuits, Vol.39, No.9, pp.1468 – 1476, Sept. 2004.
[21]. M. Waltari and K.A.I. Halonen, “1-V 9-bit pipelined switched-opamp ADC,” IEEE Journal of Solid-State Circuits, Vol.36, No.1, pp.129 – 134, Jan. 2001.
[22]. R.V.D. Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2nd,” Kluwer Academic Publ, pp.521 – 522, March. 2003.
[23]. S. Sheikhaei, S. Mirabbasi and A. Ivanov, “A 0.35μm CMOS comparator circuit for high-speed ADC applications,” IEEE International Symposium of Circuits and Systems, Vol. 6, pp.6134 - 6137, May. 2005.
[24]. R. Lotfi, M. Taherzadeh-Sani, and O. Shoaei, “A 1.5-V 12-bit 75M-samples/s fully-differential low-power sample-and-hold amplifier in 0.25μm CMOS,” Electronics, IEEE International Conference of Circuits and Systems, Vol.2, pp.814 – 817, Dec. 2003.
[25]. M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, “A pseudo-class-AB telescopic-cascode operational amplifier,” International Symposium of Circuits and Systems, Vol.1, pp.737 – 740, May. 2004.
[26]. S.H. Lewis and P.R. Gray, “A Pipelined 5-Msample/s 9-bit analog-to-digital converter,” IEEE Journal of Solid-State Circuits, Vol.22, No.6, pp.954 – 961, Dec. 1987.
[27]. R. Lotfi, et al., “A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters,” International Symposium of Signals, Circuits and Systems, Vol. 2, pp.377 – 380, July. 2003.
[28]. G.W. Roberts, “Calculating distortion levels in sampled-data circuits using SPICE,” IEEE International Symposium of Circuits and Systems, Vol.3, pp.2059 – 2062. May. 1995.
[29]. C. Wulff and C. Ytterdal, “0.8V 1GHz dynamic comparator in digital 90nm CMOS technology,” NORCHIP Conference, 23rd, pp.237 – 240, Nov. 2005.
[30]. J. Wang and Y. Qiu, “Analysis and design of fully differential gain-boosted telescopic cascode opamp,” International Conference of Solid-State and Integrated Circuits Technology, Vol.2, pp.1457 – 1460, Oct. 2004.
[31]. S. Runhua and L. Peng, “A gain-enhanced two-stage fully-differential CMOS op amp with high unity-gain bandwidth,” IEEE International Symposium of Circuits and Systems, vol.2, pp.428 – 431, May. 2002.
[32]. B. Shem-Tov, M. Kozak, and E.G. Friedman, “A high-speed CMOS op-amp design technique using negative Miller capacitance,” IEEE International Conference of Electronics, Circuits and Systems, pp.623 – 626, Dec. 2004.
[33]. A. Boni, A. Pierazzi, and C. Morandi, “A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS,” IEEE Journal of Solid-State Circuits, Vol.36, No. 2, pp.195 – 203, Feb. 2001.
[34]. H. Cheng-Chung, and W. Jieh-Tsorng, “A 33 mW 12-bit 100 MHz sample-and-hold amplifier,” IEEE Asia-Pacific Conference of Proceedings, pp.169 – 172, Aug. 2002.
[35]. L. Sumanen, et al., “CMOS dynamic comparators for pipeline A/D converters,” IEEE International Symposium of Circuits and Systems, Vol.5, pp.157 - 160, May. 2002.
[36]. S. Mathur, et al., “A 115mW 12-bit 50 MSPS pipelined ADC,” IEEE International Symposium of Circuits and Systems, Vol.1, pp.913 – 916, May. 2002.
[37]. B.M. Min, et al., “A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC,” IEEE Journal of Solid-State Circuits, Vol.38, No.12, pp.2031 – 2039, Dec. 2003.
[38]. P. Jong-Bum, “A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth,” IEEE Journal of Solid-State Circuits, Vol.39, No.8, pp.1335 – 1337, Aug. 2004.
[39]. N. Wang, P. Zhou, “A 10-b 100-MS/s 95mW CMOS ADC IP With Emphasis on Layout Matching,” IEEE Asian Conference of Solid-State Circuits, pp.355 – 358, Nov. 2006.
[40]. I. Echere and M. Boris, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling,” IEEE Journal of Solid-State Circuits, Vol.42, No.4, pp.748 – 756. April. 2007.
[41]. Gubbins, D.; Bumha Lee; Hanumolu, P.K.; Un-Ku Moon, “A Continuous-time Input Pipeline ADC,” IEEE 2008 Custom Integrated Circuits Conference (CICC), pp.169 – 172. 2008.
[42]. Van de Vel, H.; Buter, B.A.J.; van der Ploeg, H.; Vertregt, M.; Geelen, G.J.G.M.; Paulus, E.J.F.; “A 1.2-V 250-mW 14-b 100-MS/s Digitally Calibrated Pipeline ADC in 90-nm CMOS,” IEEE Journal of Solid-State Circuits, Vol.44, No.4, pp.1047 – 1056. April. 2009.
[43]. Lee, K.-H.; Kim, Y.-J.; Kim, K.-S.; Lee, S.-H.; “14 bit 50 ms/s 0.18 μm CMOS pipeline ADC based on digital error calibration,” IEEE Electronics Letters, Vol.45, No.21, pp. 1067 – 1069. 2009.
[44]. Varzaghani, A.; Yang, C.-K.K.; “A 4.8 GS/s 5-bit ADC-Based Receiver with Embedded DFE for Signal Equalization,” IEEE Journal of Solid-State Circuits, Vol.44, No.3, pp. 901 – 915. March. 2009.
[45]. Oliveira, J.; Goes, J.; Figueiredo, M.; Santin, E.; Fernandes, J.; Ferreira, J.; “An 8-bit 120-MS/s Interleaved CMOS Pipeline ADC Based on MOS Parametric Amplification,” IEEE Transactions on Circuits And Systems—II: Express Briefs, VOL. 57, NO. 2, pp. 105 – 109. February. 2010.
[46]. H.C. Kim, D.K. Jeong and W. Kim, “A partially switched-opamp technique for high-speed low-power pipelined analog-to-digital converters,” IEEE Transactions of Circuits and Systems I: Regular Papers, Vol.53, No.4, pp.795 – 801, April. 2006.
[47]. B. Sedighi, et al., “A 1.5V 150MS/s current-mode sample-and-hold circuit,” European Conference of Circuit Theory and Design, Vol.2, pp.91 – 94. Sept. 2005.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 54.221.69.42
論文開放下載的時間是 校外不公開

Your IP address is 54.221.69.42
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code