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博碩士論文 etd-0804111-140955 詳細資訊
Title page for etd-0804111-140955
論文名稱
Title
一個新穎垂直式非揮發性多位元能陷式記憶體之特性研究
Study of a Novel Vertical Non-volatile Multi-Bit SONOS Memory
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
93
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-15
繳交日期
Date of Submission
2011-08-04
關鍵字
Keywords
記憶體、SONOS、垂直式、無接面、多位元
multi-bit, Junctionless, SONOS, vertical, memory
統計
Statistics
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中文摘要
在本論文中,我們提出一個製程簡單的嵌入式閘極垂直電晶體的架構(Vertical Embedded Gate, VEG),以模擬軟體ISE TCAD 以及Silvaco TCAD 來驗證。在基本元件特性上我們使用無接面 (Junctionless)技術並且搭配額外的兩個側壁式閘極形成無接面的虛三閘極元件(Junctionless Pseudo Tri-Gate Vertical MOSFET, PTGV)得到很好的電性,例如次臨界擺幅 (Subthreshold Swing, S.S.)近乎於理想值60 mV/dec、Ion/Ioff 電流比為1010 在極短通道8 nm 的條件下達到。此外,我們提出之嵌入式閘極垂直式元件架構也可以被應用在非揮發式記憶體上,使用嵌入式閘極垂直元件架構製造矽- 氧化矽- 氮化矽- 氧化矽- 矽(SONOS)元件有幾項優點,除了擁有三個源極、汲極 (S/D)端與兩個通道可以獨立操作之外,兩個氮化矽層 (Nitride)更提供了元件多位元操作的可能性,經過元件在三個S/D 端施加偏壓的方式不同,可以達到兩位元與四位元的操作,一個元件擁有多位元的特性在本論文中被實現。
Abstract
In this thesis, a simple vertical embedded gate (VEG) MOSFET process is proposed and demonstrated by using simulation tools of ISE TCAD and Silvaco TCAD. In fundamental electrical characteristics, we employed junctionless technology and two extra sidewall spacer gates to fabricate the Junctionless Pseudo Tri-Gate Vertical (JPTGV) MOS.
According to numerical analysis, the excellent electrical characteristics such as subthreshold swing (S.S.) ~ 60 mV/dec and Ion/Ioff ~ 1010 are achieved at short gate length (Lg) 8 nm. In additional, our proposed VEG structure can also be applied for non-volatile memory. Using VEG structure to fabricate the SONOS devices have some features, it not only has three source/drain (S/D) terminals and two channels which can be operated independently, but also has two silicon nitride trap layers to provide the possible operation of multi-bit. We can apply different voltage in these three S/D terminals to achieve two bits or even four bits operation, thus the device has multi-bit characteristic is realized in this thesis.
目次 Table of Contents
第一章 導論 ............................................................................................. 1
1.1 背景與重要性 .............................................................................. 1
1.2 非揮發式記憶體元件簡介 .......................................................... 2
1.3 動機 .............................................................................................. 4
第二章 非揮發性記憶體之操作方式與原理 ....................................... 11
2.1 基本特性 .................................................................................... 11
2.1.1 通道熱載子注入寫入機制 ............................................. 12
2.1.2 Fowler-Nordheim 穿隧寫入機制 ................................... 14
2.1.3 Fowler-Nordheim 穿隧抹除機制 ................................... 17
2.1.4 熱電洞注入抹除機制 ..................................................... 18
2.2 資料保持時間 ............................................................................ 19
2.3 耐久度 ........................................................................................ 20
2.4 干擾 ............................................................................................ 21
第三章 元件設計、規劃與製程 ........................................................... 23
3.1 元件設計 .................................................................................... 23
3.2 理想製程 .................................................................................... 24
3.2.1 雙通道無接面的閘極控制電阻器 ................................. 24
3.2.2 多位元垂直式的SONOS 記憶體 .................................. 26
3.3 實際製程 .................................................................................... 28
3.3.1 雙通道無接面的閘極控制電阻器 ................................. 28
3.3.2 多位元垂直式的SONOS 記憶體 .................................. 30
第四章 結果與討論 ............................................................................... 32
4.1 使用模型 .................................................................................... 32
4.2 模擬分析 .................................................................................... 33
4.2.1 雙通道無接面的閘極控制電阻器 ................................. 33
4.2.2 多位元垂直式的SONOS 記憶體 .................................. 40
4.3 實驗結果 .................................................................................... 58
第五章 總結 ........................................................................................... 69
5.1 結論 ............................................................................................ 69
5.2 未來展望 .................................................................................... 69
參考文獻 ..................................................................................................... 71
附錄 ............................................................................................................. 77
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