近年來，手持式智慧型設備的普及化。因應消費者的需求及製程技術的快速進步；電路的設計雖然越來越龐大複雜，但面積及功率的消耗卻須越來越小。以現今的電路設計，其層次已是百萬個邏輯閘以上的系統晶片(System on Chip，SoC)，因此電子設計自動化(Electronic Design Automatic，EDA)工具的輔助在開發及驗證(Verification)的流程上是不可或缺的重要角色。
緣於教育部國家型科學計畫，使得「三維圖形加速系統」有晶片下線(Chip Tape-out)的必要。在前段(Front-End)的流程中，硬體方面以硬體描述語言(Hardware Description Language， HDL)來設計各個子模組─矽智財(Silicon Intellectual Property， SIP)；軟體方面以開發應用程式介面(Application Interface，API)及編譯器(Compiler)為主軸。最後，再將這些設計整合進AMBA匯流排成為一SoC系統。因系統整合的工程龐大且需考慮的面向較多，增加了驗證的複雜度和效率；因此需藉由一些方法來輔助以達成快速驗證，使晶片開發時程能達到上市時機（Time-to-Market）的目標。
有別於前段的流程，後段(Back-End)的流程較重視製程技術的影響以及電子設計自動化工具的使用來輔助開發驗證。本論文主要探討後段流程中所面臨的問題，及如何使晶片在設計流程上仍能保持一定的穩定度和效能，最後透過國研院晶片中心(Chip Implementation Center，CIC)與台灣積體電路公司(Taiwan Semiconductor Manufatring Company，TSMC)的簽約委託來達成晶片下線為目標。於2011年8月及2014年2月達到兩顆SoC晶片的下線，分別為3DG ES1.0 SoC和3DG ES2.0 SoC。
本研究以打通後段的開發暨驗證流程為目標，過程中所遇到的困難與挑戰將詳述於本論文中，此經驗將給予後續接手者能更順遂的實作出晶片。

In recent years, the popularity of handheld smart devices.In order to the demand of consumer and rapid progress of the technological process; Although the design is becoming complex, but the area is still delicate and thin.Today’s circuit design, its level have been SoC which consist of more than millions logic gates, so the Electronic Design Automation tools has a indispensable role in the design and verification flow.
Due to the National Science Program, "3D graphics acceleration system" had to chip tape-out. In the front-end process, hardware through the Hardware Description Language to design the sub module-Silicon Intellectual Property; software was developing the Applition Interface and Compiler. Finally, we integrated the ARM7-like CPU and AMBA which were proposed from our laboratory into a system. Since the system integration was a huge task need to considering more, increasing the complexity and performance of verification. Therefore, it was achieved rapid verification by the FPGA Emulation and SystemC, and it's much easier to meet the constraint of time to market.
Unlike the Front-End process, Back-End processes more emphasis on the impact of process technology and the use of electronic design automation tools to assist in the development of validation. This paper mainly discusses the problems faced by the segment of the process, and how to make the chip in the design process can still maintain a certain degree of stability and effectiveness, and finally through the Chip Implementation Center (CIC) and Taiwan Semiconductor Manufatring Company (TSMC) signing downline commission to achieve the target wafer. In August 2011 and February 2014 reached two SoC chip off the assembly line, respectively 3DG ES1.0 SoC and 3DG ES2.0 SoC.
In this Research, the goal is pass the back-end implementation and verification process. The difficulties and challenges encountered in the process will be detailed in this thesis, this experience will give follow-up over who can make more success in the real chip.

論文審定書+i
論文聲明書+ii
致謝+iii
中文摘要+v
Abstract+vi
Chapter 1. Introduction+1
1.1 Research Background+1
1.2 Research Motivation+2
1.3 Research Range and Goal+4
1.4 Contribution+5
1.5 Thesis Architecture+5
Chapter 2. Related Works+6
2.1 Interconnection+6
2.1.1 AMBA AHB+6
2.1.2 AMBA AXI+8
2.1.3 Feature Comparison of AXI and AHB+9
2.2 Referenced flow of IC Design+10
Chapter 3. OpenGL ES2.0 3D Graphics SoC+12
3.1 Overview+12
3.2 Architecture+13
3.3 Interface Definition+16
3.4 Specification+18
Chapter 4. Verification+19
4.1 Test Pattern of OpenGL ES2.0 3DG SoC+20
4.2 Verification Coverage+24
4.3 Automatic Verification Mechanism+27
Chapter 5. Synthesis Strategy+29
5.1 Polishing up the RTL Integration+29
5.2 The problems occur during Synthesis stage+30
5.2.1 Tolerance of Incomplete Design Data+30
5.2.2 Memory Usage+34
5.3 Synthesis Optimization+42
Chapter 6. Layout Strategy+45
6.1 IO Planning+46
6.2 Memory Place+57
6.3 Debug and Design Rule Checking+60
Chapter 7. Chip Testing+66
7.1 Introduction+66
7.2 Testing Flow+68
7.3 Pattern Generating+70
Chapter 8. Conclusion+72
Chapter 9. Future Work+73
Reference+74
AppendixA Verification Environment Setting+75
A.1 Pre-Layout Gate-Level+75
A.1.1 Introduction+75
A.1.2 Logic Synthesis+77
A.1.3 Gate-level Simulation and Verification+82
A.1.4 Case study for the 3DG ES2.0 SoC+82
AppendixB Script for Synthesis+86
AppendixC File Architecture+109

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