隨著數位化產品的迅速發展，對類比與數位訊號的轉換和處理也日益備受重視，然而面對速度越來越快的數位產品，也延伸出對高速的類比數位轉換器的需求，又如果加上可攜性產品的應用，也顯現出類比數位轉換器功率消耗大小的重要性，而在類比數位轉換器裡，以取樣保持電路為重要元件，故學生以高速且低電壓、低功率的概念去設計實作取樣保持電路。
本論文採用UMC 90nm製程技術，分析取樣保持電路的架構，設計實做一個10位元，100百萬取樣速率且低功率取樣保持電路。採用class AB型的放大器來實作。

The digital product increases widely and vastly. We need a converter to change analog signal to digital one. However, the requirement of analog-to-digital converter is rising due to progress of DSP (Digital Signal Processor). In most ADC structure there have an important building block called the front-end sample-and-hold circuit (SHA) . I will design and implement a high speed and low power sample and hold circuit.
In this thesis, the circuits are designed with UMC 90nm 1P9M CMOS process and 1.2V of supply voltage. The speed and resolution of SHA are 100Ms/s and 10bits individually. The circuit is implemented with class AB amplifier.

Chapter 1 Introduction……………………………………………………………….1
Reading Guidelines………………………………………………………..2

Chapter 2 Sample and hold circuit(SHA)…………………………………………….3
2.1 Introduction of SHA…………………………………………….3
2.2.1 Configuration 1……………………………………….3
2.2.2 Configuration 2……………………………………….4
2.2.3 Configuration 3……………………………………….4

Chapter 3 Performances Definition and Strategies…………………………………...7
3.1 Performances Definition…………………………………………7
3.1.1 Acquisition Time………………………………………8
3.1.2 Quantization error……………………………………...8
3.1.3 Integral Nonlinearity (INL)…………………………....9
3.1.4 Differential Nonlinearity (DNL)………………………9
3.1.5 Signal-to-Noise Ratio(SNR)………………………….10
3.1.6 Signal-to-Noise and Distortion Ratio(SNDR)………..10
3.1.7 Effective Number of Bits (ENOB)…………………...10
3.1.8 Spurious-Free Dynamic Range (SFDR)……………...10
3.1.9 Charge injection………………………………………11
3.1.10 Clock Feed through…………………………………..12
3.1.11 Gain Error…………………………………………….12
3.1.12 Hold settling time…………………………………….13
3.2 Strategies………………………………………………………..13
3.2.1 Dummy switches……………………………………..13
3.2.2 Bottom plate sampling………………………………..14
3.2.3 Differential bottom plate sampling…………………...15
3.2.4 Complementary Switches…………………………….16

Chapter 4 Key design of SHA…………………………………..................................17
4.1 Introduction……………………………………………………..17
4.2 KT/C Noise……………………………………………………...17
4.3 switch……………………………………………………………19
4.3.1 On-Resistance………………………………………...19
4.3.2 Charge Injection……………………………………...20
4.3.3 Clock Feedthrough…………………………………...21
4.4 Operational Amplifier…………………………………………..22
4.4.1 Operational Amplifier structure………………………22
4.4.2 Single-Stage Opamp………………………………….22
4.4.3 Two-Stage Opamp……………………………………23
4.4.4 Telescopic Cascode Opamp…………………………..24
4.4.5 Regulated Cascode(Gain Boosting)………………….24
4.4.6 Folded Cascode………………………………………25
4.4.7 Comparison…………………………………………..27
4.4.8 DC Gain………………………………………………27
4.4.9 Phase Margin…………………………………………28
4.4.10 Unity Gain Frequency………………………………..29
4.4.11 Slew rate (SR)………………………………………..30
4.4.12 A Example: Folded Cascode Amplifier………………30

Chapter 5 The implementation of SHA………………………………………………33
5.1 Switch…………………………………………………………...33
5.2 Booster circuit…………………………………………………..36
5.3 Amplifiers……………………………………………………….37
5.4 Bias voltage generator circuit…………………………………...44
5.5 Bandgap circuit………………………………………………….45
5.6 Clock generator circuit………………………………………….47
5.7 Simulation of SHA……………………………………………...48
Chapter 6 Conclusion………………………………………………………………...50
References...................................................52

[1] Y. M. Lin, B. Kim, and P. R. Gray, “A 13b 2.5MHz self-calibrated pipelined A/D con-verter in 3-mm CMOS,” IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, April 1991.
[2] S. H. Lewis, et al., “10b 20Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, March 1992.
[3] L. A. Bienstman and H. J. DeMan, “An eight-channel 8bit microprocessor compatible nmos D/A converter with programmable scaling,” IEEE J. Solid-State Circuits,vol. 15, pp. 1051-1059, Dec. 1980.
[4] R. C. Yen and P. R. Gray, “A MOS switched-capacitor instrumentation amplifier,” IEEE J. Solid-State Circuits, vol. 17, no. 6, December 1982, pp. 1008-1013.
[5] K. L. Lee, “Low Distortion Switched Capacitor Filters”, Electron. Res. Lab. Memo M86/12, University of California, Berkeley, 1986.
[6] A. N. Karanicolas, H. S. Lee, and K. L. Bacrania, “A 15b 1MS/s digitally self-cali-brated pipeline ADC”, in ISSCC Dig. Tech. Papers, Feb. 1993, pp. 60-61.
[7] T. B. Cho and P. R. Gray, “A 10bit, 20MS/s, 35mW pipeline A/D converter,” in Proc. IEEE Custom Integrated Circuits Conf., May 1994, pp 23.2.1-23.2.4.IEEE Custom Integrated Circuits Conf., May 1994, pp 23.2.1-23.2.4.
[8] Y.M. Lin, “Performance limitations on high-resolution video-rate analog-digital interfaces,” Memo. No. UCB/ERL M90/55, 19 June, 1990.
[9] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Co.Inc, pp.420 – 421, pp.37 – 39, 2001.
[10] Y. Chouia, et al., “14 b, 50 MS/s CMOS front-end sample and hold module dedicated to a pipelined ADC,” Midwest Symposium of Circuits and Systems, Vol.1, pp.353 – 361, July. 2004.
[11] C.J.B. Fayomi, G.W. Roberts, and M. Sawan, “Low-voltage CMOS analog bootstrapped switch for sample-and-hold circuit: design and chip characterization,” IEEE International Symposium of Circuits and Systems, Vol. 3, pp.2200 – 2203, May. 2005.
[12] T.N. Andersen, et al., “A cost-efficient high-speed 12-bit pipeline ADC in 0.18um Digital CMOS,” IEEE Journal of Solid-State Circuits, Vol.40, No.7, pp.1506 – 1513, July. 2005.
[13] T. Glad, L. Ljung, “Reglerteknik – Grundläggande teori”, Studentlitteratur, 2nd edition 2000, ISBN 91-44-17892-1.
[14] D. Johns, K. Martin, “Analog integrated circuit design”, John Wiley & Sons, 1997, ISBN 0-471-14448-7.
[15] S. Mallya and J.H. Nevin, “Design procedures for a fully differential folded-cascode CMOS operational amplifier,” IEEE Journal of Solid-State Circuits, Vol.24, No. 6, pp.1737 – 1740. Dec. 1989.
[16] G.W. Roberts, “Calculating distortion levels in sampled-data circuits using SPICE,” IEEE International Symposium of Circuits and Systems, Vol.3, pp.2059 – 2062. May. 1995.
[17] R. Lotfi, et al., “A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters,” International Symposium of Signals, Circuits and Systems, Vol. 2, pp.377 – 380, July. 2003.
[18] T. Cho, “Low-Power Low-Voltage Analog-to-Digital Conversion Techniques Using Pipelined Architectures,” UC Berkeley PhD Thesis, 1995.
[19 ]M. Mohajerin, C. Chen and E. Abdel-Raheem, “A new 12-b 40 ms/s, low-power, low-area pipeline ADC for video analog front ends,” IEEE Pacific Rim Conference, pp.597 – 600, Aug. 2005.
[20] D. M. Monticelli, “A quad CMOS single-supply op-amp with rail-to-rail output swing,” IEEE J. Solid-State Circuits, vol. SC-21, no. 6, pp.1026–1034, Jun. 1986.
[21] De Langen and H. J. Huising, “Compact low-voltage power-efficient operational amplifier cells for VLSI,” IEEE J. Solid-State Circuits, vol. 33, no. 10, pp. 1482–1496, Oct. 1998.
[22] F. You, S. H. K. Embabi, and E. Sanchez-Sinencio, “Low-voltage Class-AB buffers with quiescent current control,” IEEE J. Solid-State Circuits, vol. 33, no. 6, pp. 915–920, May 1998.
[23] A. Torralba, R. G. Carvajal, J. Martinez-Heredia, and J. Ramírez An-gulo, “Class-AB output stage for low voltage CMOS op-amps with ac-curate quiescent current control,” Electron. Lett., vol. 36, no. 21, pp.1753–1754, Oct. 2000.
[24] J. Ramirez-Angulo, R. G. Carvajal, J. Tombs, and A. Torralba, “A simple technique for op-amp continuous-time 1 V supply operation,” Electron. Lett., vol. 35, no. 4, pp. 263–264, Feb. 18, 1999.
[25] S. Rabii and B. A. Wooley, “The Design of Low-Voltage, Low Power Sigma Delta Modulators”. Norwell, MA: Kluwer, 1999, ch. 6, p. 126.
[26] M. Taherzadeh-Sani, R. Lotfi, and O. Shoaei, “A pseudo-class-AB telescopic-cascode operational amplifier,” International Symposium of Circuits and Systems, Vol.1, pp.737 – 740, May. 2004.
[27] J. Ramírez-Angulo, Ramón G. Carvajal, Juan A. Galán, “A Free But Efficient Low-Voltage Class-AB Two-Stage Operational Amplifier” IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 53, NO. 7, JULY 2006
[28] R. Lotfi, M. T. Sani, and O. Shoaei “A 1.5-V 12-BIT 75M-SAMPLES/S FULLY-DIFFERENTIAL LOW-POWER SAMPLE-AND-HOLD AMPLIFIER IN 0.25-um CMOS,” International Symposium of Circuits and Systems, Vol.1, pp.737 – 740, May. 2004.
[29] C. Wulff and C. Ytterdal, “0.8V 1GHz dynamic comparator in digital 90nm CMOS technology,” NORCHIP Conference, 23rd, pp.237 – 240, Nov. 2005.
[30] J. Wang and Y. Qiu, “Analysis and design of fully differential gain-boosted telescopic cascode opamp,” International Conference of Solid-State and Integrated Circuits Technology, Vol.2, pp.1457 – 1460, Oct. 2004.
[31] Cheng-Chung Hsu and Jieh-Tsorng Wu “A 33-mW 12-Bit 100-MHz Sample-and-Hold Amplifier” Department of Electronics Engineering National Chiao-Tung University, Hsin-Chu 300, Taiwan
[32] M. Yavari, O. Shoaei, and A. Rodriguez-Vazquez “Systematic and Optimal Design of CMOS Two-Stage Opamps with Hybrid Cascode Compensation” 3-9810801-0-6/DATE06 © 2006 EDAA
[33] J. Rosenfeld, M. Kozak, and Eby G. Friedman “A BULK-DRIVEN CMOS OTA WITH 68 dB DC GAIN” 0-7803-8715-5/04/$20.00 ©2004 IEEE.
[34] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, Member, IEEE “A CMOS Bandgap Reference Circuit with Sub-1-V Operation” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY 1999
[35] K. Honda, Student Member, IEEE, M. Furuta, Member, IEEE, and S. Kawahito, Senior Member, IEEE “A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 4, APRIL 2007