由於現代的手持行動裝置越來越先進，體積越來越小，然而對於效能的要求卻一直的提高，這表示需要更多的功率消耗。因此，如何減低這些裝置的功率消耗，使得目前的電池可以負荷，就成為我們必須面對的重要議題。目前在系統層級的階段，並沒有一個足夠成熟、商業性的軟體可以提供給研發人員一個好的平台來評估系統的功率消耗。所以本論文提出一個可以在系統層級觀察並且計算功率消耗的功率估計環境，讓SOC開發人員可以在系統層級的階段，來進行功率的估計。本論文所提出的功率估計架構，可以讓使用者訂定自己研發的元件之功率計算公式(功率模型)，另外也提供了CPU，以及memory、bus、等功率計算的公式可使用。除了提供功率模型以及方便修改功率模型的程式之外，也提供了一個電源管理元件。此元件可以讓開發人員使用不同的power management policy在此power management元件來進行系統的電源管理，因此可以有效的判斷此policy的有效程度。本論文所提供的架構皆架設在SystemC的環境之中，使用者可以快速的更換功率模型，以及power management policy，因此可以提供給開發人員更方便、更快速的系統功率估計以及架構改善的開發方式，來進行系統的功率估計測試，並且比較不同的功率模型的優缺點，以及power management policy的優缺點。

The modern handheld devices have become smaller and more complex nowadays. However, the requirements for its performance and functions have also become higher, which means that it needs more power consumption. Therefore, the essential issue that we are facing now is to reduce the power consumption in order to fit the capacity of the batteries. In the current system level design, there is no presentable commercial tool for designers to estimate the power consumption of the system. This thesis proposes a framework for system level power estimation, which allows the users to add the power models of these modules developed by them in the system level. Moreover, the power models of CPU, memory and bus are also provided. Besides the power models and convenient method to modify these models, a power management unit is also provided. With this unit, the designers can use different power management policies to manage the system’s power consumption and decide its power efficiency. In this thesis, the framework is constructed under the environment of SystemC, so the users can alternate the power model and power management policy rapidly. By using this framework, the designers can more conveniently and rapidly estimate the system’s power consumption and improve the system’s architecture. Therefore, it can fast examine the advantages and disadvantages of various power models and power management policies.

1 INTRODUCTION 1
1.1 MOTIVATION 1
1.2 CONTRIBUTION 2
1.3 ORGANIZATION 2
2 BACKGROUND AND RELATIVE WORK 3
2.1 ESL(ELECTRONIC SYSTEM LEVEL) DESIGN 3
2.2 TLM (TRANSACTION LEVEL MODELING) 5
2.3 LOW POWER TECHNIQUES 9
2.3.1 Clock gating 11
2.3.2 Power management 13
2.3.3 System level power estimation 16
2.4 SYNCHRONIZE PLATFORM 19
3 SYSTEM LEVEL POWER ESTIMATION 20
3.1 THE POWER ESTIMATION UNIT 20
3.2 THE METHODS OF POWER CONSUMPTION CALCULATION 28
3.3 POWER MANAGEMENT UNIT 31
3.4 MULTI-LAYER AHB SYSTEM 32
4 EXPERIMENT ENVIRONMENT AND RESULT 35
4.1 EXPERIMENT ENVIRONMENT 35
4.1.1 RAM power model: 38
4.1.2 Bus power model 40
4.1.3 CPU power model 41
4.1.4 ASIC power model 43
4.2 EXPERIMENTAL RESULT 45
4.2.1 Power management result 45
4.2.2 Uniform Window-based Predictor 5 (UW5): 46
4.2.3 Uniform Window-based Predictor 1+5 (UW1+5): 49
4.2.4 Proportional-Integral-Derivative controller 52
4.3 SYNCHRONIZE PLATFORM 56
5 CONCLUSION 60

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