為了改善之前所提出稱為QSC，以QEMU與SystemC為基礎之虛擬平臺上的模擬效能及使用OSCI TLM-2.0標準的便利性，本篇論文提出一套新的方式整合OSCI TLM-2.0與QSC。透過將OSCI TLM-2.0的匯流排移至匯流排功能模組(BFM)之外，所提出的方法不只加速模擬速度也使得新增OSCI TLM-2.0元件(IP)至QSC上更為方便使用。實驗結果顯示所提出的方法與之前的作比較，其模擬速度的加速比率平均值為2.8到3.255倍。

In order to improve the performance of simulation and the convenience of use with OSCI TLM-2.0 Standard on QEMU and SystemC based virtual platform we proposed previously called QSC, this thesis presents a novel approach for integrating OSCI TLM-2.0 with QSC. By moving the OSCI TLM-2.0 interconnect bus outside of the Bus Function Model (BFM), the proposed approach can not only accelerate the simulation speed but also make it easy to add OSCI TLM-2.0 based Intellectual Properties (IPs) to the QSC. Experimental results show that the proposed approach can speed up all the simulations by a factor from 2.8 up to 3.255 on average when compared with the previous approach.

論文審定書 i
摘要 iii
ABSTRACT iv
List of Figures vii
List of Tables viii
List of Listings ix
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Chapter 2 Related Work 4
2.1Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1 QEMU-SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.1.1 QSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1.1.2 OSCI SystemC . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1.2 Transaction Level-modeling and OSCI TLM-2.0 . . . . . . . . . . . . 9
2.1.2.1 Transation Level-modeling . . . . . . . . . . . . . . . . . . 9
2.1.2.2 OSCI TLM-2.0 . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.3 AMBA 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 The Other Simulation Platforms . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3 OSCI TLM-2.0 Interconnect Interface 16
3.1Design of the OSCI TLM-2.0 Interconnect . . . . . . . . . . . . . . . . . . . . 16
3.1.1 Functional Module Design . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1.2 Communacation Deisgn . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.3 Parallel Processing Model . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Proposed Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2.1 Coding Style and Core Interface . . . . . . . . . . . . . . . . . . . . . 21
3.2.2 Sockets and Payloads . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.2.3 Adapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2.4 Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2.5 Bundled Arbitration Model . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.6 Test Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 4 Experimental Results 32
4.1 Simulation Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.2 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.2.1 The Original QSC-CCA Model . . . . . . . . . . . . . . . . . . . . . 33
4.2.2 The Proposed Model: The OSCI TLM-2.0 Interconnect Interface Model 34
4.2.3 The Parallel Processing Model: The OSCI TLM-2.0 Interconnect
Interface with SystemC BFM model . . . . . . . . . . . . . . . . . . . . 35
4.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Chapter 5 Conclusion and Future Works 44
5.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Bibliography 46

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