Responsive image
博碩士論文 etd-0805111-101326 詳細資訊
Title page for etd-0805111-101326
論文名稱
Title
一新穎具有共享摻雜區域之高集積密度互補式金氧半反向器
A Novel High Integration-Density CMOS Inverter with Unique Shared Contact
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
127
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2011-07-15
繳交日期
Date of Submission
2011-08-05
關鍵字
Keywords
互補式金氧半反向器、穿隧場效電晶體、超薄本體、矽覆絕緣、無接面金氧半場效電晶體、閘極控制之N-I-P電晶體
TFET, JL MOSFET, UTB, SOI, CMOS, Gated N-I-P transistor
統計
Statistics
本論文已被瀏覽 5646 次,被下載 0
The thesis/dissertation has been browsed 5646 times, has been downloaded 0 times.
中文摘要
一種具有高集積密度、製程步驟簡單之新穎互補式金氧半(Novel CMOS)反向
器已經被發展出來,此種新穎互補式金氧半反向器是利用閘極控制之N-I-P 電晶體
(Gated N-I-P transistor)取代原本傳統互補式金氧半(CMOS)反向器之正型金氧半場
效電晶體(PMOSFET)負載器,以解決因為寬度補償做造成的集積密度降低的問題。
由於閘極控制之N-I-P 電晶體,其獨特的摻雜結構與輸出電流隨著閘極偏壓增加而
降低的特性,有利於當作邏輯閘之負載器,並搭配上不同種類之驅動器,如:負
型金氧半場效電晶體(NMOSFET)、負型穿隧場效電晶體(NTFET)或超薄本體(UTB)
之無接面金氧半場效電晶體(JL NMOSFET)…等,構成具獨特共享摻雜區域(N-type)
與共享輸出節點之新穎互補式金氧半反向器。本研究主要探討由負型穿隧場效電
晶體及超薄本體無接面金氧半場效電晶體當作驅動器,並以閘極控制N-I-P 電晶體
當作負載器之新穎互補式金氧半反向器及其特性與分析。根據結果,本研究所提
出之新穎互補式金氧半反向器有正確的邏輯特性,且延遲時間較互補式穿隧場效
電晶體(CTFET)改善了87.2 %,也較無接面互補式金氧半反向器(JL CMOS)改善了
43.2 %,這是因為閘極控制之N-I-P 電晶體其獨特操作機制且為雙載子傳輸的緣故。
此外,由於驅動器與負載器兩元件之間的摻雜區域(同為N-type)相同,可共享形成
輸出端,且為矽覆絕緣(SOI)結構,兩元件之間無須物理性隔離結構,可以大幅提
升集積密度,佈局面積較傳統互補式金氧半反向器節省54.1 %,較矽覆絕緣互補
式金氧半反向器節省40.1 %,並降低製程步驟。因此,我們相信,本研究所提出
之具高集積密度、製程步驟簡易之新穎互補式金氧半反向器可以成為未來下世代
互補式金氧半反向器的最佳候選之一。
Abstract
A novel CMOS inverter has been proposed. We utilize gated N-I-P transistor to
replace the conventional PMOSFET for solving the problem of width compensation.
Also, we carefully investigate and analyze the non-conventional CMOS characteristics
with NTFET and/or UTB JL MOSFET as driver and gated N-I-P transistor as a load.
According to the results, our proposed novel CMOS inverter has correct logic behavior
and its delay time is reduced about 87.2 % when compared with the CTFET. Also, our
proposed CMOS still can get a 43.2 % reduction in delay time when compared with JL
CMOS. In addition, because of the N-type output drain node and the SOI structure, our
proposed CMOS does not need any physical isolation technique, thereby improving the
packing density. Our proposed CMOS indeed obtain a 54.1 % reduction of the total area
compared with the conventional CMOS. Our proposed CMOS also can achieve a 40.1
% reduction in the total area when compared with the SOI-based CMOS. More
importantly, due to the reduced process steps, the cost reduction can be achieved. We
therefore believe that a high packing density novel CMOS inverter with reduced process
steps can become one of the contenders for future CMOS scaling.
目次 Table of Contents
第一章 導論 1
1.1 背景 1
1.1.1 改變結構 3
1.1.2 改變材料 10
1.1.3 使用應力技術 13
1.2 動機 17
第二章 物理機制與元件操作原理 19
2.1 物理機制 19
2.1.1 穿隧場效電晶體(TFET)物理與操作機制 19
2.1.2 無接面負型金氧半場效電晶體(JL NMOSFET)物理與操作機制 21
2.1.3 閘極控制N-I-P電晶體(Gated N-I-P Transistor)物理與操作機制 22
2.2 新穎邏輯元件操作理論與原理 25
2.2.1. 傳統互補式金氧半邏輯閘操作理論與原理 25
2.2.2. 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 29
2.2.3. 以無接面負型金氧半場效電晶體當作驅動器以及以閘極控制N-I-P電晶體當作負載器構成之新穎具共享摻雜區域與超薄本體互補式金氧半邏輯閘 31
第三章 元件架構設計與製作 37
3.1 元件架構設計 37
3.1.1 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 37
3.1.2 由無接面負型金氧半場效電晶體及閘極控制N-I-P電晶體所構成,具有超薄本體結構與共享摻雜區域之新穎互補式金氧半反相器 46
第四章 結果與討論 49
4.1 元件模擬之物理模型 49
4.2 電性分析與討論 51
4.2.1 以負型穿隧場效電晶體及閘極控制N-I-P電晶體所構成之新穎具共享摻雜區域互補式金氧半反相器 51
4.2.2 由無接面負型金氧半場效電晶體及閘極控制N-I-P電晶體所構成,具有超薄本體結構與共享摻雜區域之新穎互補式金氧半反相器 65
4.3 基本邏輯電路模擬 69
4.3.1 反或閘 (NOR Gate) 69
4.3.2 反及閘 (NAND Gate) 75
4.3.3 環形震盪器(Ring Oscillator) 82
4.4 實作結果 84
第五章 新穎互補式金氧半反向器之優點 85
5.1 載子遷移率與延遲時間 85
5.2 製程步驟與集積密度 88
第六章 結論與未來展望 93
6.1 結論 93
6.2 未來展望 94
參考文獻 95
附錄 101
參考文獻 References
[1]. F. M. Waelass and C. T. Sah, “Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes,” IEEE International Solid- State Circuit Conference, pp. 32-33, 1963.
[2]. D. A. Neamen, “Semiconductor Physics and Devices: Basic Principles,” The McGraw- Hill Company, 3rd edition, pp. 507-509.
[3]. S. M. Sze, K. K. Ng, “Physics of Semiconductor Devices,” A John Wiley & Sons, Inc., Publication, 3rd edition, pp. 328-338.
[4]. A. Bathtold, P. Hadley, T. Nakanishi, and C. Dekker, “Logic circuits with carbon nanotube transistors,” Science, vol. 294, no. 5545, pp. 1317-1320, November, 2001.
[5]. C. Chen, D. Xu, E. S. W. Kong, and Y. Zhang, “Multichannel Carbon-Nanotube FETs and Complementary Logic Gates With Nanowelded Contacts,” IEEE Electron Device letters, vol. 27, no. 10, pp. 852-855, October, 2006.
[6]. S. C. Rustagi, Senior Member, IEEE, N. Singh, W. W. Fang, K. D. Buddharaju, S. R. Omampuliyur, S. H. G. Teo,C. H. Tung, Senior Member, IEEE, G. Q. Lo, N. Balasubramanian, and D. L. Kwong, “CMOS Inverter Based on Gate-All-Around Silicon-Nanowire MOSFETs Fabricated Using Top-Down Approach,” IEEE Electron Device Letters, vol. 28, no. 11, pp. 1021-1024, November, 2007.
[7]. P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, O. Thomas, O. Cueto, N. Bouzaida, D.Fleury2, A. Amara1, S. Deleonibus and O. Faynot, “Advances in 3D CMOS Sequential Integration,” IEEE International Electron Devices Meeting, vol. 14, no. 1, pp. 345-348, 2009.
[8]. A. Pal, A. B. Sachid, H. Gossner, Member, IEEE, and V. R. Rao, Senior Member, IEEE, “Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits,” IEEE Transactions on Electron devices, vol. 58, no. 4, pp. 1045-1053, April, 2011.
[9]. J.P. Colinge, C.W. Lee, A. Afzalian, N. Dehdashti, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.M. Kelleher, B. McCarthy and R. Murphy, “SOI Gated Resistor: CMOS without Junctions,” IEEE International SOI Conference, 2009.
[10]. J. B. Kuo, Member, IEEE, W. C. Lee, and J. H. Sim, “Back-Gate Bias Effect on the Subthreshold Behavior and the Switching Performance in an Ultrathin SOI CMOS Inverter Operating at 77 and 300 K,” IEEE Transactions on Electron devices, vol. 39, no. 12. pp. 2781-2790, December, 1992.
[11]. Q. Liu, A. Yagishita, N. Loubet, A. Khakifirooz, P. Kulkarni, T. Yamamoto, K. Cheng, M. Fujiwara, J. Cai, D. Dorman, S. Mehta, P. Khare, K. Yako, Y. Zhu, S. Mignot, S. Kanakasabapathy, S. Monfray, F. Boeuf, C. Koburger, H. Sunamura, S. Ponoth, A. Reznicek, B. Haran, A. Upham, R. Johnson, L. F. Edge, J. Kuss, T. Levin, N. Berliner, E. Leobandung, T. Skotnicki, M. Hane, H. Bu, K. Ishimaru, W. Kleemeier, M. Takayanagi, B. Doris, R. Sampson, “Ultra-Thin-Body and BOX (UTBB) Fully Depleted (FD) Device Integration for 22nm Node and Beyond,” Symposium on VLSI Technology, pp. 61-62, 2010.
[12]. J. Feng, Y. Liu, P. B. Griffin, and J. D. Plummer, Fellow, IEEE, “Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate,” IEEE Electron Device Letters, vol. 27, no. 11, pp. 911-913, November, 2006.
[13]. O. M. Alatise, Member, IEEE, K. S. K. Kwa, S. H. Olsen, and A. G. O’Neill, Fellow, IEEE, “Improved Analog Performance in Strained-Si MOSFETs Using the Thickness of the Silicon–Germanium Strain-Relaxed Buffer as a Design Parameter,” IEEE Transactions on Electron Devices, vol. 56, no. 12, pp. 3041-3048, December, 2009.
[14]. S. Oh, Student Member, IEEE, and H. S. Philip Wong, Fellow, IEEE, “A Physics-Based Compact Model of III–V FETs for Digital Logic Applications: Current–Voltage and Capacitance–Voltage Characteristics,” IEEE Transactions on Electron Devices, vol. 56, no. 12, pp. 2917-2924, December, 2009.
[15]. M. Heyns, C. Adelmann, G. Brammertz, D. Brunco, M. Caymax, B. D. Jaeger, A. Delabie, G. Eneman, M. Houssa, D. Lin, K. Martens, C. Merckling, M. Meuris, J. Mittard, J. Penaud, G. Pourtois, M. Scarrozza, E. Simoen, S. Sioncke and W. E Wang, “Ge and III/V devices for advanced CMOS,” International Conference on Ultimate Integration of Silicon, pp. 83-86, 2009.
[16]. G. Doornbos and M. Passlack, Fellow, IEEE, “Benchmarking of III–V n-MOSFET Maturity and Feasibility for Future CMOS,” IEEE Electron Device Letters, vol. 31, no. 10, pp. 1110-1112, October, 2010.
[17]. A. Majumdar, C. Ouyang, Senior Member, IEEE, S. J. Koester, Senior Member, IEEE, and W. Haensch, Senior Member, IEEE, “Effects of Substrate Orientation and Channel Stress on Short-Channel Thin SOI MOSFETs,” IEEE Transactions on Electron Devices, vol. 57, no. 9, pp. 2067-2072, September, 2010.
[18]. I. Ok, K. Akarvardar, S. Lin, M. Baykan, C. D. Young, P.Y. Hung, M. P. Rodgers, S. Bennett, H. O. Stamper, D. L. Franca, J. Yum, J. P. Nadeau, C. Hobbs, P. Kirsch, P. Majhi, R. Jammy, “Strained SiGe and Si FinFETs for High Performance Logic with SiGe/Si stack on SOI,” IEEE International Electron Devices Meeting, vol. 34, no. 2, pp. 776-779, 2010.
[19]. W. Y. Choi, Member, IEEE, B. G. Park, Member, IEEE, J. D. Lee, Member, IEEE, and T. J. King Liu, Fellow, IEEE, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, August, 2007.
[20]. Y. Khatami, Student Member, IEEE, and K. Banerjee, Senior Member, IEEE, “Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits,” IEEE Transactions on Electron Devices, vol. 56, no. 11, pp. 2752-2761, November, 2009.
[21]. R. Gandhi, Z. Chen, N. Singh, Senior Member, IEEE, K. Banerjee, Senior Member, IEEE, and S. Lee, “Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤ 50 mV/decade) at Room Temperature,” IEEE Electron Device Letters, vol. 32, no. 4, pp. 437-439, April, 2011.
[22]. K. Boucart, W. Riess, and A. M. Ionescu, “Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs,” IEEE Electron Device Letters, vol. 30, no. 6, pp.656-658, June, 2009.
[23]. N. N. Mojumder, Student Member, IEEE, and K. Roy, Fellow, IEEE, “Band-to-Band Tunneling Ballistic Nanowire FET: Circuit-Compatible Device Modeling and Design of Ultra-Low-Power Digital Circuits and Memories,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2193-2201, October, 2009.
[24]. C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Applied Physics Letters, vol. 94, no.5, pp. 053511-053511-2, February, 2009.
[25]. J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A. M. Kelleher, B. McCarthy and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, pp. 225-229, March, 2010.
[26]. Y. Ōmura, “A lateral, unidirectional, bipolar-type insulated-gate transistor-A novel semiconductor device,” Applied Physics Letters, vol. 40, no.6, pp. 528-529, March, 1982.
[27]. Y. Ōmura, “Lateral Unidirectional Bipolar-type Insulated-Gate Transistors,” Japanese Journal of Applied Physics, vol. 22, no.1, pp. 263-266, 1983.
[28]. J. T. Lin, H. H. Chen, K. Y. Lu, C. H. Sun, Y. C. Eng, C. H. Kuo, P. H. Lin, T. Y. Lai, F. L. Yang, “Design theory and fabrication process of 90nm Unipolar-CMOS,” Silicon Nanoelectronics Workshop, 2010.
[29]. Y. Gao, T. Low, M. Lundstrom, “Possibilities for VDD = 0.1V Logic Using Carbon-Based Tunneling Field Effect Transistors,” Symposium on VLSI Technology, pp. 180-181, 2009.
[30]. S. Agarwal, G. Klimeck, and M. Luisier, “Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors,” IEEE Electron Device Letters, vol. 31, no. 6, pp. 621-623, June, 2010.
[31]. S. Mookerjea, Student Member, IEEE, R. Krishnan, Student Member, IEEE, S. Datta, Senior Member, IEEE, and V. Narayanan, Senior Member, IEEE, “Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation,” IEEE Transactions on Electron Devices, vol. 56, no. 9, pp. 2092-2098, September, 2009.
[32]. K. Cheng, A. Khakifirooz, P. Kulkarni, S. Kanakasabapathy, S. Schmitz, A. Reznicek, T. Adam, Y. Zhu, J. Li, J. Faltermeier, T. Furukawa, L. F. Edge, B. Haran, S. C. Seo, P. Jamison, J. Holt, X. Li, R. Loesing, Z. Zhu, R. Johnson, A. Upham, T. Levin, M. Smalley, J. Herman, M. Di, J. Wang, D. Sadana, P. Kozlowski, H. Bu, B. Doris, and J. O’Neill, “Fully Depleted Extremely Thin SOI Technology Fabricated by a Novel Integration Scheme Featuring Implant-Free, Zero-Silicon-Loss, and Faceted Raised Source/Drain,” Symposium on VLSI Technology, pp. 212-213, 2009.
[33]. A. Majumdar, Z. Ren, S. J. Koester, Senior Member, IEEE, and W. Haensch, Senior Member, IEEE, “Undoped-Body Extremely Thin SOI MOSFETs With Back Gates,” IEEE Transactions on Electron Devices, vol. 56, no. 10, pp. 2270-2276, October, 2009.
[34]. K. Cheng, A. Khakifirooz, P. Kulkarni, S. Ponoth, J. Kuss, L. F. Edge, A. Kimball, S. Kanakasabapathy, S. Schmitz, A. Reznicek, T. Adam, H. He, S. Mehta, A. Upham, S. C. Seo, J. L. Herman, R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, S. Fan, H. Bu, D. K. Sadana, P. Kozlowski, J. O'Neill, B. Doris, G. Shahidi, “Extremely Thin SOI (ETSOI) Technology: Past, Present, and Future,” IEEE International SOI Conference, 2010.
[35]. J. P. Colinge, “Silicon- on- Insulator Technology: Materials to VLSI,” Kluwer Academic Publishers, pp. 91-106.
[36]. K. Y. Lu, J. T. Lin, H. H. Chen, Y. C. Eng, C. H. Tai, C. H. Chen, Y. C. Chang, and Y. H. Fan, “Characterization for Novel Non-traditional CMOS Inverter Composed of a Junctionless NMOSFET and a Gated N+-N--P Transistor,” International Symposium on Next-Generation Electronics, pp. 243-245, 2010.
[37]. User’s Manual, ISE-TCAD 10.0, 2004.
[38]. Y. Yang, X. Tong, L. T. Yang, P. F. Guo, L. Fan, and Y. C. Yeo, “Tunneling Field-Effect Transistor: Capacitance Components and Modeling,” IEEE Electron Device Letters, vol. 31, no. 7, pp. 752-754, July, 2010.
[39]. S. M. Kang, Y. Leblebigi “CMOS Digital Integrated Circuits: Analysis and Design,” The McGraw- Hill Company, 3rd edition, pp. 239-241.
[40]. P. F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis, D. Schmitt-Landsiedel, W. Hansch, “Complementary Tunneling Transistor for Low Power Application,” Solid-State Electronics, vol. 48, no. 12, pp. 2281-2286, December, 2004.
[41]. E. R. Hsieh and S. S. Chung, “A New Type of Inverter with Juctionless (J-Less) Transistors,” Silicon Nanoelectronics Workshop, 2010.
[42]. T. Sakurai, A. Matsuzawa, T. Douseki, “Fully-depleted SOI CMOS Circuits and Technology for Ultra-Low Power Applications,” Springer Verlag, pp. 6-7.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:自定論文開放時間 user define
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 3.17.74.227
論文開放下載的時間是 校外不公開

Your IP address is 3.17.74.227
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code