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博碩士論文 etd-0806107-105832 詳細資訊
Title page for etd-0806107-105832
論文名稱
Title
五千兆赫自動選頻相鎖迴路
5 GHz Phase Lock Loop with Auto Band Selection
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
80
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2007-07-27
繳交日期
Date of Submission
2007-08-06
關鍵字
Keywords
相頻偵測器、雙模數前置除頻器、電壓控制振盪器、相鎖迴路、自動選頻器
dual-modulus prescaler, phase-frequency detector., Voltage-controlled oscillator, auto band-selection, Phase lock loop
統計
Statistics
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The thesis/dissertation has been browsed 5634 times, has been downloaded 0 times.
中文摘要
本論文採用TSMC 0.18μm 1P6M CMOS製程,設計一個適用於WCDMA且具有自動選頻功能之除整數(Integer-N)頻率合成器。本論文的頻率合成器包含相頻偵測器(PFD)、電荷幫浦(CP)、低通迴路濾波器(LPF)、自動選頻器(ABS)、電壓控制振盪器(VCO)以及含雙模數前置除頻器(dual-modulus prescaler)之pulse-swallow divider。在pulse-swallow divider方面,本論文採用Yuan和Svensson提出九個電晶體架構的TSPC正反器來設計雙模數前置除頻器以工作於高頻區並降低功率消耗及減少晶片面積。最後再提出一個可自動選頻的機制使我們可以更方便且精確的控制輸出頻率,並且可以有效的降低頻率合成器因製程偏移或溫度差異所產生的頻飄誤差。
Abstract
This thesis presents the CMOS integer-N frequency synthesizer for 5 GHz WCDMA applications with 1.8V power supply. The frequency synthesizer is fabricated in a TSMC 0.18μm CMOS 1P6M technology process. The frequency synthesizer consists of a phase-frequency detector, a charge pump, a low-pass loop filter, a voltage control oscillator, an auto-band selection, and a pulse-swallow divider. In pulse-swallow divider, this thesis use true single phase clock DFF proposed by Yuan and Svensson to work on high frequency region and to save the circuit area and power. This thesis also proposes an auto-band selection circuit to control the output frequency more precise and easier, and it can also reduce the frequency drift effect caused by technology process or temperature variation.
目次 Table of Contents
CHAPTER 1 INTRODUCTION 1
1.1 Motivation 1
1.2 Thesis Organization 3
CHAPTER 2 THE CONCEPTS OF FREQUENCY SYNTHESIZER 4
2.1 General Concepts 4
2.1.1 Sidebands 5
2.1.2 Lock Time 6
2.2 Types of Frequency Synthesizer 7
2.2.1 The Digital Synthesizer 7
2.2.2 The Direct Synthesizer 8
2.2.3 The Indirect Synthesizer 9
2.3 Frequency Synthesizer 11
2.3.1 Basic Concepts 11
2.3.2 Voltage-Controlled Oscillator 12
2.3.3 Phase Frequency Detector (PFD) 17
2.3.4 Charge Pump and Loop Filter 21
2.3.5 Frequency Divider 23
CHAPTER 3 The Proposed Phase Lock Loop 26
3.1 Introduction 26
3.2 VCO (voltage controlled oscillator) 27
3.2.1 Topology and design procedure 27
3.2.2 Memory-Reduced Tail Transistor VCO 29
3.2.3 Switched Capacitors 36
3.2.4 Performance of VCO 56
3.3 Frequency Divider 38
3.3.1 Dual-modulus prescaler divide-by-16/17 40
3.4 Phase-Frequency Detector 41
3.5 Charge Pump 44
3.6 Auto Band-Selection 48
3.6.1 Conception review 48
3.6.2 Circuits algorithm 48
3.6.3 Circuit combination 51
CHAPTER 4 SIMULATION RESULT 53
4.1 RF Model and CMOS process 53
4.2 Simulation of VCO 53
4.3 Simulation of Divide-by-16/17 prescaler 58
4.4 Simulation of pulse-swallow divider 59
4.5 Simulation of Auto Band-Selection circuit 60
4.6 Simulation of PFD and CP 60
4.7 Simulation of PLL 61
4.8 Layout of Chip 63
CHAPTER 5 CONCLUSION AND FUTURE WORK 64
5.1 Conclusion 64
5.2 Future Work 65
Reference 66
參考文獻 References
[1] J. Craninckx, and M.Steyaert, ”WIRELESS CMOS FREQUENCY SYNTHESIZER DESIGN,” KLUWER ACADEMIC PUBLISHERS, 1998.
[2] C. Samori, S. Levantino, V. Boccuzzi, ”A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications,” IEEE Conf. on Custom Integrated Circuits, pp. 201-204, May 2001.
[3] Avanindra Madisetti, Alan Y. Kwentus, and Alan N. Willson, ” A 100-MHZ, 16-b, Direct Digital Frequency Synthesizer with 100-dBc Spurious-Free Dynamic Range,” IEEE J. Solid-state Circuits, Vol. 34, No. 8, pp. 1034-1043, Aug. 1999.
[4] Mozhgan Mansuri, Dean Lin, and Chih-Kong Ken Yang, ” Fast Frequency Acquisition Phase-Frequency Detector for Gsamples/s Phase-Locked Loops,” IEEE J. Solid-state Circuits, Vol. 37, No. 10, pp. 1331-1334, Oct. 2002.
[5] H. Chang and J. Wu, ”A 723-MHz 17.2-mW CMOS programmable counter,” IEEE J. Solid-state Circuits, Vol. 33, pp. 1572-1575, Oct. 1998.
[6] T. Aytur and B. Razavi, “A 2 GHz, 6 mW BiCMOS frequency synthesizer,” in Proc. Int. Solid-state Circuit Conf., pp. 264-265, 1995.
[7] C. Diorio, T. Humes, J. K. Notthoff, G. Chao, A. Lai, J. D. Hydo, M. Kinits, and A. Oki, ”A low-noise, GaAs/AlGaAs, microwave-frequency synthesizer IC,” IEEE J. Solid-state Circuits, Vol. 33, pp. 1306-1312, Sept. 1998.
[8] P.Larsson, “High-Speed architecture for a programmable frequency divider and a dual-modulus prescaler,” IEEE J. Solid-state Circuits, Vol.31, pp. 744-748, May 1996.
[9] N. Krishnapura and P. R. Knight, “A 5.3-GHz programmable divider for HiPerLAN in 0.25 μm CMOS,” IEEE J. Solid-state Circuits, Vol. 35, pp. 1019-1024, July 2000.
[10] Lam. C, Razavi. B, “A 2.6-GHz/5.2-GHz frequency synthesizer in 0.4-μm CMOS technology,” IEEE J. Solid-state Circuits, Vol. 35, pp. 788-794, May 2000.
[11] C.C. Boon, M.A. Do, K.S. Yeo, J.G. Ma, X.L. Zhang, “RF CMOS low-phase-noise LC oscillator through memory reduction tail transistor” IEEE J. Solid-state Circuits, Vol. 51, Issue 2, pp. 85-90, Feb 2004.
[12] Klumperink, E.A.M.; Gierkink, S.L.J.; van der Wel, A.P.; Nauta, B., “Reducing MOSFET 1/f noise and power consumption by switched biasing”, IEEE J. Solid-state Circuits, Vol. 35, Issue 7, pp. 994-1001, July 2000.
[13] Rael, J.J.; Abidi, A.A., “Physical processes of phase noise in differential LC oscillators”, Proc. of the IEEE 2000, Conf. on Custom Integrated Circuits, 2000. CICC, No. 21-24, pp.569-572, May 2000.
[14] D. Ham and A. Hajimiri, “Concepts and methods in optimization of integrated LC VCOs,” IEEE J. Solid-State Circuits, Vol. 36, pp. 896-909, June 2001.
[15] S. Kogan, Electronic Noise and Fluctuations in Solids, Cambridge, U.K.: Cambridge Univ. Press, 1996.
[16] J. C. Chang, A. A. Abidi, and C. R. Viswananthan, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Trans. Electron Devices, Vol. 41, pp. 1965-1971, Nov. 1994.
[17] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, “A unified model for flicker noise in metal-oxide-semiconductor field-effect transistors,”IEEE Trans. Electron Devices, Vol. 37, pp. 654-665, Mar. 1990.
[18] E. A. M. Klumperink, S. L. J. Gierkink, A. P. van derWel, and B. Nauta, “Reducing MOSFET 1=f noise and power consumption by switch biasing,” IEEE J. Solid-State Circuits, Vol. 35, pp. 994-1001, July 2000.
[19] S. L. J. Gierkink, E. A. M. Klumperink, A. P. van derWel, G. Hoogzaad, E. van Tuijl, and B. Nauta, “Intrinsic 1=f device noise reduction and its effect on phase noise in CMOS ring oscillators,” IEEE J. Solid-State Circuits, Vol. 34, pp. 1022-1025, July 1999.
[20] P. Andreani, S. Mattisson, “On the use of MOS varactors in RF VCOs”, Digital Object Identifier, Vol. 35, Issue 6, pp. 905-910, June 2000.
[21] C. Toumazou, G. Moschytz, and B. Gilbert, Trade-offs in analog circuit design: the designer’s companion, Dordrecht, The Nether lands: Kluwer Academic Publisher, 2002.
[22] Robert C. Chang and Lung-Chih Kuo, “A New Low-Voltage Charge Pump Circuit for PLL,” IEEE International Symposium on Circuits and Systems ISCAS, pp.701-703, May 2000
[23] Tord Johnson, Ali Fard, and Denny Aberg, “An Improved Low Voltage Phase-Frequency Detector with Extended Frequency Capability,” Circuits and Systems, 2004. MWSCAS ’04. The 2004 47th Midwest Symposium on Vol. 1, pp. 181-184, July 2004.
[24] Fard, A.; Johnson, T.; Aberg, D.; “A low power wide band CMOS VCO for multi-standard radios”, IEEE Conf. on Radio and Wireless Conference, pp. 79-82, Sept 2004.
[25] Chung-Yu Wu; Chi-Yao Yu; “A 0.8 V 5.9 GHz wide tuning range CMOS VCO using inversion-mode bandswitching varactors”, IEEE Conf. Circuits and Systems, 2005. ISCAS 2005, Vol. 5, pp. 5079-5082, May 2005.
[26] Yi-Hsien Cho; Ming-Da Tsai; Ying-Tang Chang; Huei Wang; “A Wide-band Low Noise Quadrature CMOS VCO”, IEEE Conf. Asian Solid-State Circuits, pp. 325-328, Nov. 2005.
[27] Zhou Zhujin; Li Ning; Li Wei; Ren Junyan; “A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB Receivers”, IEEE Conf. Circuits and Systems, 2007. ISCAS 2007, pp. 437-440, May 2007.
[28] Jang, S.-L.; Chuang, Y.-H.; Lee, S.-H.; Chi, L.-R.; Lee, C.-F.; “An Integrated 5–2.5-GHz Direct-Injection Locked Quadrature LC VCO”, IEEE J. Microwave and Wireless Components Letters, Vol. 17, Issue 2, pp. 142-144, Feb. 2007.
[29] Benzard Razavi, “RF MICROELECTRONICS”, PRENTICE HALL PTR, 1998.
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