目前的系統單晶片(System On Chip, SOC)設計，大多是同(異)質的多核心架構。然而多核心架構將使得核心之間的溝通次數與資料量增加，匯流排結構成為影響整個多核心系統效能相當重要的問題。核心之間藉此架構存取記憶體，而為了達到資料同步處理的目的， 主要的處理機制常以Pooling或Interrupt方式完成。但Pooling會增加BUS的traffic，而Interrupt處理時往往造成時脈的浪費。為了改善此缺失，我們以常用於嵌入式系統之AMBA匯流排協定為基礎，設計並實現具有Rendezvous的資料同步處理機制於AHB架構中，命名為Rendezvous of Advanced High performance Bus(RAHB)。RAHB機制主要於核心與BUS介面之間增加Slave port與操作模式選擇模組，核心透過操作模式選擇模組控制Master與Slave的傳輸，除了原有AHB的主從式傳輸外，增加了與核心之間Rendezvous的傳輸機制，其中Slave port具有傳輸緩衝之功能，核心間執行傳輸時，若目的核心尚未備妥，傳輸資料可由Master port轉至本機端的Slave port等待存取，等待目的核心備妥後，由目的核心的Master port主動執行傳輸。Rendezvous傳輸不透過Pooling或Interrupt達到資料同步處理的目的，因而減少了BUS的traffic與Interrupt時處理的時間浪費，直接在指令階層上達到核心間執行process的同步溝通，改善多核心處理器之間的傳輸效率，增加整體執行效能。根據模擬的結果顯示，Rendezvous模式下的RAHB傳輸與以Pooling執行同步溝通方式的AHB傳輸效率，於執行各種不同長度的資料溝通平均可增加將近約50%的傳輸效率。執行測試程式時，則可增加約30~40%的執行效能。

In current chip multi-processors (CMPs), the on-chip network is a major factor affecting overall system performance. Different kinds of communication protocols vary from different communication architectures of current SOC designs. For example, the AMBA is master-slave architecture, which transacts and communicates the data of between the two CORE (Master) through the Memory (Slave). The architecture cost long time for load and store with memory. Hence, this paper design and implement a Rendezvous protocol on AMBA architecture, which is called Rendezvous of Advanced High performance Bus (RAHB), to let two processors can communicate with each other without memory reference overheads. The RAHB is compatible with the AHB architecture, and add Rendezvous communication protocol in the AMBA architecture to perform the direct transmission of data. Without referring the memory, the RAHB can improve the efficiency of communication in multi-core. For experimental evaluation, we evaluate the performance between RAHB and AHB, RAHB speedup (B/s) is average up to 50% for different data length and performance up 30% to 40% for executing test program.

摘要 i
ABSTRACT iii
第一章 緒論 1
1.1. 研究動機 1
1.2. 研究目標 2
1.3. 論文架構 3
第二章 相關研究 4
2.1. Inter-processor Communication 4
2.1.1. 點對點的直接連結(peer-to-peer) 6
2.1.2. 共享匯流排(Share BUS) 7
2.1.3. 晶片網路(Network On Chip, NOC) 11
2.2. Multi-Core Communications Platform 12
2.2.1. UltraSPARC T2 12
2.2.2. DaVinci平台 13
2.2.3. Cell Broadband Engine (CELL BE) 15
2.2.4. NUMA與UMA架構 17
2.3. Network Latency and Bandwidth 18
2.4. Rendezvous 傳輸機制 20
2.5. ARM相容指令集之五階管線處理器-ARMVP 22
2.6. DMA控制器與ARM Processor 24
2.7. 結果與討論 25
第三章 支援Rendezvous溝通機制之AMBA架構設計 26
3.1. Rendezvous AHB架構分析 27
3.2. Master與Slave 28
3.3. Operation mode select模組 34
3.3.1. 傳輸方式 36
3.4. 其餘AHB模組 38
3.5. RAHB相容於AHB之傳輸與回應機制 40
3.6. 結果與討論 44
第四章 模擬與分析 45
4.1. AHB傳輸協定 45
4.1.1. ARM EASY Module 46
4.1.2. Synopsys DesignWare AHB Verification 47
4.1.3. AHB on chip bus protocol checker 48
4.2. 建立RAHB平台 52
4.3. 相容於AHB協定之測試 55
4.4. 模擬分析比較 60
4.4.1. Latency與Effective Bandwidth 60
4.4.2. 傳輸效率分析比較 62
AHB Time of flight(Ideal) 62
4.4.3. RAHB使用率 65
4.5. RAHB與ARMVP整合以FPGA測試實現 66
4.5.1. 與ARMVP整合 67
4.6. 結果與討論 75
第五章 結論 76
參考文獻 77

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