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論文名稱 Title |
具有數位浮水印功能之嵌入式影像編解碼器VLSI設計與實作 VLSI Design and Implementation of Embedded Zerotree Wavelet Image CODEC with Digital Watermarking |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
78 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2000-07-28 |
繳交日期 Date of Submission |
2000-08-07 |
關鍵字 Keywords |
超大型積體電路、浮水印、嵌入式零樹小波 VLSI, Watermark, EZW, Embedded Zerotree Wavelet |
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統計 Statistics |
本論文已被瀏覽 5731 次,被下載 6495 次 The thesis/dissertation has been browsed 5731 times, has been downloaded 6495 times. |
中文摘要 |
本論文提出Embedded Zreotree Wavelet演算法及修改過 EZW演算之硬體架構,其有規律性、模組性、擴充性和具 備嵌入及偵測浮水印之功能等優點。設計方法:針對演 算法原理及輸出入資料的順序加以研究、分析,利用佇 列、堆疊等記憶體單元及控制電路,實現其演算法及浮 水印之功能。修改過的EZW硬體架構較原始EZW架構在記 憶體需求上,減少一半以上,其效能與原始之架構相去 不遠。除此之外,也提出整體性的轉換編解碼器系統之 架構。其適合應用在即時壓縮高解析度影像(HDTV)、 MPEG-4系統或網路QoS系統。 |
Abstract |
The paper proposes that Embedded Zreotree Wavelet algorithm and the architecture of the modified EZW algorithm will have the property of regularity, modularity ,and scalablity, and also posses the function , which can allow a detected watermark to be embedded. The methods to realize the algorithm and the function of watermark are to analyze the theory of algorithm and the order of output and input data and then to use queue and stack, the unit of memory, and the control of circuit. The modified EZW architecture needs a half less memory units than the original one, and functions nearly as effective as the original architecture. Besides, this paper points out that the whole architecture of the transform CODEC system can be applied properly to HDTV, MPEG-4 system, or QoS network. |
目次 Table of Contents |
CHAPTER 1 導論 1 1.1 論文架構 1 1.2 動機 1 1.3 相關論文 2 CHAPTER 2 相關研究 3 CHAPTER 3 演算法 8 3.1 零樹(ZEROTREE)編碼演算法 8 3.1.1. 連續、漸進式(SUCCESSIVE APPROXIMATION)量化 8 3.1.2. EMBEDDED ZEROTREE CODER(EZW) 10 3.1.3. SET PARTITIONING IN HIERACHICAL TREES(SPIHT) 14 3.1.4. 範例 17 3.2 MODIFIED EMBEDDED ZEROTREE WAVELET 24 3.3 浮水印(WATERMARKING) 28 CHAPTER 4 記憶體分析 30 CHAPTER 5 架構 35 5.1 EZW ENCODER 硬體架構 35 5.2 EZW DECODER 硬體架構 44 5.3 MODIFIED EZW ENCODER硬體架構 53 5.4 MODIFIED EZW DECODER 硬體架構 57 5.5 EZW ENCODER 系統架構 59 5.6 EZW DECODER 系統架構 68 CHAPTER 6 結果與討論 71 6.1 EZW CODEC之架構 71 6.2 MODIFIED EZW CODEC之架構 73 6.3 EZW與MODIFIED EZW 架構之比較 74 CHAPTER 7 結論與未來展望 76 7.1 結論 76 7.2 未來與展望 77 參考文獻 78 |
參考文獻 References |
[1] J.M. Shapiro,"Embedded image coding using zerotrees of wavelet Coefficients",IEEE Trans , Signal Processing,Vol. 41 ,No. 12.Dec 1993. [2] A. Said and W. A. Pearlman,"A new fast and efficient image codec based on set partitioning in hierarchical tree", IEEE Trans. Circuits and Systems foe Video Technology, Vol.6, No.3,jun 1996. [3] L. Ang, H. N. Cheung and K. Eshraghian, "VLSI Architecture For Embedded Zerotree Wavelet Algorithm", Circuits and System 1999 ISCAS '99 .Proc of the 1999 IEEE International Symposium on Vol 1 pp 141-144 1999 [4] L.-M. Ang, et al.,"VLSI Architecture for Very High Resolution Scalable Video Coding Using the Virtual Zero Tree", Proc. of IEEE Workshop on Signal Processing Systems, pp. 131-140, Oct.1999. [5] J.Bae and V. K. Prasanna,"A Fast and Area-efficient VLSI architecture for embedded image coding", Proceedings International Conference on Image Processing, Vol 3, Oct. 1995 [6] B.Vanhoof, M. Peon, G. Lafruit, J. Bormans, L. Nachtergaele, I. Bolsens "A Scalable Architecture for MPEG-4 Wavelet Quantization",Journal of VLSI Signal Processing System for Signal,Image,and Video Technology, Vol. 23,No. 1,Oct 1999 [7] F. W. Wheeler, W. A. Pearlman "SPIHT Image Compression Without Lists", ICASSP 2000,CDROM IV2047-2050 |
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