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博碩士論文 etd-0807100-134215 詳細資訊
Title page for etd-0807100-134215
論文名稱
Title
以開關電晶體為主之自動最佳化邏輯合成器
Automatic Optimization in Pass-Transistor-Based Logic Synthesizer
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
45
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2000-07-28
繳交日期
Date of Submission
2000-08-07
關鍵字
Keywords
開關電晶體、邏輯合成器、最佳化
logic synthesizer, pass-transistor, optimization
統計
Statistics
本論文已被瀏覽 5648 次,被下載 4540
The thesis/dissertation has been browsed 5648 times, has been downloaded 4540 times.
中文摘要
在本篇論文中,我們設計了一個合成器來合成各種組合電路,建立以開關電晶體為主的電路,輸入為布林函數的格式,可以同時輸入數個函數讓硬體共享,針對不同的電路特性利用RC delay model做最佳化,節省面積與提高速度,最後輸出為Verilog gate-level code與HSPICE netlist,以提供Verilog-in和模擬使用。最佳化所需的執行時間短,可快速的得到最好的結果。
Abstract
In this thesis, An automatic optimization logic synthesizer in pass-transistor-based is developed for logic mapping of the combinational circuits. The format of inputs is Boolean functions with expression of sum of product and we can input several functions for hardware sharing at the same time. Depending the difference of circuits, we use the RC delay model to do optimization for both area and speed performance. The final, output is Verilog gate-level code and HSPICE netlist that provide Verilog-in for automatic place-and-route and simulation. It only needs little executing time for searching the best result and we can quickly gate it.
目次 Table of Contents
第1章 導論 1
1.1 論文架構 1
1.2 動機說明 1
第2章 電路 4
2.1 簡介 4
2.2 CMOS電路 4
2.3 CPL電路 5
2.4 SRPL電路 6
2.5 DCVSPG電路 7
2.6 EEPL電路 8
2.7 DPL電路 9
2.8 LEAP電路 10
2.9 電路分析與比較 11
第3章 邏輯合成器 17
3.1 簡介 17
3.2 BDD TREE化簡 18
3.3 加入反相器 22
3.3.1 不同層級加入P-latch inverter的影響 23
3.3.2 P-latch inverter 24
3.4 邏輯合成器流程圖 29
第4章 最佳化 30
4.1 簡介 30
4.2 RC DELAY MODEL 30
4.3 電晶體寬度選擇 31
4.3.1 方法一 32
4.3.2 方法二 33
4.3.3 方法三 34
4.3.4 比較 36
4.4 順序選擇 37
第5章 結果比較 40
5.1 簡介 40
5.2 HSPICE 最佳化結果比較 40
5.2.1 C4 40
5.2.2 C8 41
5.2.3 C16 42
5.3 討論 42
第6章 結論與未來工作 44
6.1 結論 44
6.2 未來工作 44
第7章 參考文獻 45

參考文獻 References
[1] S.B. Akers, “Binary decision diagram,” IEEE Trans.Compt.,vol.C-27, No. 10, pp. 509-516, June. 1978
[2] K.Yano, Y.Sasaki, K.Rikino,and k.Seki , “Top-down pass-transistor logic d esign,” IEEE JSSC, vol. 31, No. 6, pp. 792-803, June. 1996.
[3] K. Yano, T. Yamanaka, T. Nishida. M. Saito, K. Shimohigashi, and Shimizu, “ A 3.8 ns CMOS 16X16 multiplier using complementary pass-transistor logic,” IEEE JSSC, pp. 388-395, Apr. 1990.
[4] Kuo-Hua Wang and Ting Ting Hwang, “Boolean matching for incompletely specified functions,” IEEE Trans. Comput. Computer-Aided Design, pp. 161-166, Reb.
[5] N. H. E. Weste and K. Eshraghian, Principles of CMOS VLSI Design. Reading, MA : Addison-Wesley, 1985.
[6] F. Lai and W. Hwang, “Design and Implementation of Differential Cascode Voltage Switch with Pass-Gate(DCVSPG)Logic for High Performance Digital Systems,” IEEE JSSC, pp. 563-573, Apr. 1997.
[7] M. Suzuki, N. Ohkubo, T. Yamanaka. A. Shimizu, and K. Sasaki, ”A 1.5 ns 32 b CMOS ALU in double pass-transistor logic,” IEEE JSSC, pp. 1145-1150, Nov. 1993 .
[8] Wayne Wolf , Modern VLSI Design a System Approach.
[9] A. Parameswar, et. al. “A Swing Restored Pass-Transistor Logic-Based Multiply and Accumulate Circuit for Multimedia Application,” IEEE JSSC, pp. 804-809, June 1996.
[10] J. S. Yeh, Logic/Circuit synthesizer Based on High Performance Pass-Transistor Cell Library, July 1998
[11] D. Y. Chen, Logic/Circuit synthesizer Based on Low-Complexity Pass-Transistor Cell Library, Aug. 1999
[12] M. Song, etal., “Design Methodology for High Speed and Low Power Digital Circuits with Energy Economized Pass-transistor Logic(EEPL),” Proceedings of 22nd European Solid-State Circuit Conference, Neuchatel, Switzerland, Sept. 1996, pp. 120-123
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