本論文提出了一個適用於H.264/AVC標準的高效率整合像素預測補償器，它可以提供亮度及彩度像素的inter及intra prediction功能。藉由將這兩種預測方式的演算法分解成一連串細微的運算操作，可以先用來決定出完成這些操作所需的基本數學處理單元架構。接著，考慮到參考像素的傳輸問題，整體的補償器架構使用了平行的處理單元及適當的緩衝暫存器模組，它可以動態調整適用於不同預測模式的計算排程，以符合參考像素的自然輸入順序。本論文提出的設計不但可以避免多餘的資料轉置緩衝儲存器，更重要的是抓取參考像素的資料搬移時間可以和資料的計算時間重疊。此外藉由分享inter及intra prediction的數學運算單元以及中間值的緩衝暫存器，本論文所提出的整合預測像素補償器相較於未整合之前的設計，可以節約30%的邏輯閘個數。而相較於其他文獻未經整合的研究，它也可以達到38%的邏輯閘個數節省率。
除了運算處理架構的設計，本論文也進一步探討記憶體頻寬最佳化設計的議題，因為這對inter prediction亮度樣本的處理過程特別重要。當中採用了一個基於二維快取記憶體的資料重覆使用暫存器，可以用來有效地重覆使用相同資料分割區內(Intra data partition)及相異資料分割區間(Inter data partition)的參考像素。本頻寬最佳化的設計可以輕易地整合於H.264的內插補償器硬體中以減少原本大量的記憶體存取次數。實驗結果顯示，相較於僅使用資料分割內重覆利用這項技術的最好設計而言，本論文提出的方法可以多節省20%的頻寬使用量。除此之外，我們的補償器設計效能也可以提供至高畫質電視的影像解壓縮，且可以應用於各式各樣H.264的消費性電子產品之中。

In this thesis, a high-efficient integrated pixel compensator architecture for the H.264/AVC standard has been proposed which can provide both inter and intra prediction functions for luma and chroma components of pixels. By decomposing the algorithms used for both prediction methods into small micro-operation steps, the fundamental arithmetic processing unit architecture capable for performing these operations can be first determined. Next, by considering the possible reference sample transfer issue, the overall compensator architecture will be built by using parallel processing units with some input and intermediate buffers which can be dynamically configured to perform proper computation schedules of different modes suitable for the nature input order of reference samples. The proposed design not only can avoid the additional data transposition buffer, but most importantly the data transfer time spent to fetch the reference samples can be overlapped with the data computation time. Since both arithmetic units and the intermediate data buffer for both inter and intra prediction processes have been shared, our integrated design can achieve more than 30% reduction of gate count compared with the sum of the separate designs. Our design can also lead to more than 38% saving of gate count compared with the previous designs.
In addition to the data-path design, this thesis also addresses the memory bandwidth optimization issue which is especially important for the luma interpolation process. A new data-reuse buffer design based on a two-dimensional cache architecture to explore the possible data reuse among the inter and intra partitions will be proposed. The proposed design can be easily integrated with the H.264 interpolator to reduce the enormous demand of memory access. Our experimental results shows that our saving of memory bandwidth can be 20% more than what the best design can achieve by exploring the intra-partition data reuse only. Besides, our compensator can decode the videos up to HDTV resolution, and be applied for the dedicated H.264 hardware codec for various consumer devices.

第1章 概論 1
1.1 研究動機 1
1.2 論文大綱 1
第2章 研究背景 3
2.1 Introduction to H.264/AVC 3
2.2 H.264/AVC decoding process 4
2.3 Introduction to pixel prediction 5
第3章 演算法介紹 8
3.1 Inter prediction algorithm 8
3.1.1 Luma sample interpolation algorithm 8
3.1.2 Inter prediction for different block sizes 10
3.1.3 Chroma sample interpolation algorithm 11
3.2 Intra prediction algorithm 12
3.2.1 4x4 prediction process for luma sample 12
3.2.2 16x16 prediction process for luma sample 15
3.2.3 Prediction process for chroma sample 16
第4章 演算法分析與相關研究 18
4.1 Review of inter prediction architectures 18
4.1.1 Conventional architecture 19
4.1.2 Filter design 21
4.1.3 Parallel interpolation architecture 23
4.1.4 Parallel interpolation architecture with early filtering 26
4.2 Review of bandwidth reduction techniques 27
4.2.1 Dynamic reference data for different motion vectors 28
4.2.2 Data reuse of the same partition 29
4.3 Review of intra prediction architectures 30
第5章 Integrated predictive pixel compensator design 36
5.1 Proposed inter prediction process 36
5.2 Proposed intra prediction process 40
5.2.1 Luma 4x4 prediction 40
5.2.2 Luma 16x16 prediction 44
5.2.3 Chroma 8x8 prediction 45
5.3 Inter/Intra prediction integration design analysis 46
5.4 Proposed integrated predictive pixel compensator (IPPC) 47
5.4.1 Sub-module design 48
5.4.2 Inter prediction process on IPPC 51
5.4.3 Intra prediction process on IPPC 57
第6章 Bandwidth optimization system design 62
6.1 Reference data analysis 62
6.2 Overall architecture 63
6.3 Cache design 64
6.4 Workflow 66
第7章 實作結果及效能分析 68
第8章 結論與未來目標 76
8.1 結論 76
8.2 未來目標 76

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