SAGE(Statement Analysis Grouping Evaluation)系統是針對記憶體處理器(Processor-in-Memory)結構所設計的一個以陳述(Statement)為基本分析單位的平行化程式系統。其發展目的讓程式得到最佳的平行度，使程式能充分利用到記憶體處理器結構的特性，減少程式在執行上的時間，進而提升效能。SAGE系統的實作，讓使用者輸入原始程式透過SAGE系統可直接分析轉換出適合記憶體處理器結構的程式。本論文主要是探討SAGE系統中程式碼產生器(Code Generator) 模組的實作。這個程式碼產生器模組主要是用來產生副程式、在副程式加入需傳遞的參數、在主程式加入呼叫主處理器或是記憶體處理器的函數及參數、產生可執行的程式以及產生適合該程式的模擬器介面程式，並討論測試程式經SAGE系統後，程式碼的實際情況。

SAGE (Statement Analysis Grouping Evaluation) system is a statement-based parallelizing compiler designed for PIM (Processor-in-Memory) architectures. By extracting the potential parallelism and utilizing the capabilities of PIM architectures, this system can achieve better performance of the applications. It analyzes the source codes, transforms the codes, makes good executing schedule and generates the codes which can execute on PIM architectures. This thesis focuses on the implementation of the code generator in the SAGE system. The code generator can transforms the original source codes into subroutines according to the corresponding HBG (Hyper Block Graph) and execution schedule which is determined by the other modules of SAGE system. It generates subroutines, inserts necessary arguments, determines the positions of caller and callee and generates the interface program for executing on PIM simulator. The generated codes after our code generator are also discussed.

目錄
中文摘要…………………………………………………………………I
英文摘要…………………………………………………………………II
目錄………………………………………………………………………III
圖目錄……………………………………………………………………V
表目錄……………………………………………………………………VII
第一章 簡介……………………………………………………………1
第1.1節 介紹……………………………………………………………1
第1.2節 SAGE系統………………………………………………………5
第1.3節 程式碼產生器(Code Generator)介紹………………………7
第二章 相關的研究……………………………………………………9
第2.1節 Hyper Block Graph(HBG)……………………………………9
第2.2節 HBG_Schedule…………………………………………………11
第2.3節 Polaris Internal Representation(IR)…………………12
第三章 程式碼產生器(Code Generator)之實作……………………17
第3.1節 數值傳遞………………………………………………………17
第3.2節 介面程式………………………………………………………20
第3.3節 程式碼產生器(Code Generator)的實作步驟………………23
第四章 實驗結果………………………………………………………38
第五章 結論……………………………………………………………45
附錄 Class Methods of Polaris Internal Representation……46
參考文獻…………………………………………………………………52

圖目錄
圖1-1 記憶體處理器(PIM)系統結構圖………………………………3
圖1-2 SAGE系統結構圖…………………………………………………4
圖1-3 程式碼產生器(Code Generator)的結構圖……………………8
圖2-1 超區塊圖的結構圖………………………………………………10
圖2-2 HBG_Schedule的結構圖…………………………………………11
圖2-3 Polaris Internal Representation的結構圖………………16
圖3-1-1 數值傳遞之範例程式1………………………………………19
圖3-1-2 數值傳遞之範例程式2………………………………………20
圖3-2-1 介面程式之範例………………………………………………22
圖3-3-1 程式碼產生器之範例程式……………………………………26
圖3-3-2 超區塊圖和HBG_Schedule……………………………………27
圖3-3-3 呼叫merge_piblocks()後的超區塊圖………………………28
圖3-3-4 呼叫generate_subroutine()後的Fortran 77程式………29
圖3-3-5 透過Code Generator輸出的Fortran 77程式………………30
圖3-3-6 程式碼產生器演算法…………………………………………33
圖3-3-7 合併P區塊演算法……………………………………………33
圖3-3-8 產生副程式演算法……………………………………………34
圖3-3-9 遞迴找尋參數演算法…………………………………………35
圖3-3-10 遞迴找尋表示式裡參數演算法.……………………………36
圖3-3-11 加入caller演算法…………………………………………37
圖3-3-12 產生前段介面程式演算法…………………………………37
圖3-3-13 產生後段介面程式演算法…………………………………37
圖4-1 strmm原始程式…………………………………………………40
圖4-2 經程式碼產生器產生的Fortran程式…………………………43

表目錄
表3-1 模擬器使用的函數名稱、說明與使用方式……………………23
表4-1 實驗數據…………………………………………………………44

[1] T. C. Huang, and S. L. Chu, “SAGE: A New Analysis and Optimization System for FlexRAM Architecture,” in Proc. 2nd Workshop on Intelligent Memory Systems, 2000.
[2] T. C. Huang, and S. L. Chu, “A New Analysis Approach for Intelligent Memory Systems,” in Proc. 16th International Conference on Computers and Their Applications, pp. 452-457, 2001.
[3] T. C. Huang, S. L. Chu, and L. C. Lee, “Improving Workload Balance and Code Optimization in Processor-in-Memory Systems,” in Proc. 8th International Conference on Parallel And Distributed Systems, 2001.
[4] H. L. Jean, “Designing New Scheduling Mechanisms for Processor-in-Memory Systems,” Master Thesis, Department of Electrical Engineering National Sun Yat-Sen University, 2001.
[5] H. M. Liu, “Designing a Prototype of Communication Protocol for FlexRAM Architecture,” Master thesis, Department of Electrical Engineering, National Sun Yat-Sen University, 2001.
[6] Y. B. Liu, “The Design of a New Program Decomposition Mechanism for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering National Sun Yat-Sen University, 2002.
[7] M. Y. Chen, “The Implementation of Task Evaluation and Scheduling Mechanisms for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering, National Sun Yat-Sen University, 2002.
[8] Y. Kang, W. Huang, S. Yoo, D. Keen, Z. Ge, V. Lam, P. Pattnaik, and J. Torrellas, “FlexRAM: Toward an Advanced Intelligent Memory System,” International Conference on Computer Design, 1999.
[9] M. Oskin, F. T. Chong, and T. Sherwood, “Active Page: A Computation Model for Intelligent Memory Computer Architecture,” in Proc. 25th Annual International Symposium on Computer Architecture, pp. 192 –203, 1998.
[10] J. Granacki, et al., “Data Intensive Architecture: DIVA,” http://www.isi.edu/asd/diva/, 1998.
[11] D. Patterson, T. Anderson, N. Cardwell, R. Fromm, K. Keeton, C. Kozyrakis, R. Tomas, and K. Yelick, “A Case for Intelligent DRAM,” IEEE Micro, pp. 33-44, 1997.
[12] K. Faigin, S. Weatherford, J. Hoeflinger, D. Padua, and P. Petersen, “The Polaris Internal Representation,” International Journal of Parallel Programming, 1994.
[13] J. C. Huang, “The Design of an Effective Load-Balance Mechanism for Processor-in-Memory Systems,” Master Thesis of Department of Electrical Engineering, National Sun Yat-Sen University, 2002.