除了追求更多著色器核心來達到更好的成像效能，另一個在現代圖形處理單元的重要發展趨勢是利用其強大計算能力用於通用計算的應用。本論文是將之前學術界所發展的專精於圖學成像的設計進一步的衍生為支援大量資料平行的嵌入式通用運算處理器。提出的設計是依據OpenCL(open computing language)架構中所定義的記憶體和平台模組。本論文首先將四個著色器核心組成一個compute unit，每個核心被視為一個processing element，每個processing element可以透過local memory互相的溝通。整個處理器是由多個compute unit所組成，並且可以透過global memory來交換訊息，其控制機制和原本繪圖處理器中的貼圖處理是相同的。為了使不同的執行緒在不同的processing element上執行時可以進行同步處理，OpenCL中定義了barrier，本論文也根據其規範在設計中實現。而在原本的繪圖處理器設計中已經採用的SIMD(Single Instruction Multiple Data)向量指令集處理器架構在一般運算中效能較差，因為向量所占的比率並不會那麼高。因此，我們的設計將向量處理器修改為純量處理器來達到較佳的硬體使用率。此外，同樣考慮到使用率，特殊函數運算單元也被從ALU(arithmetic logic unit )中分割出來，成為同一個compute unit中所有的processing element共享的資源。而整個處理器包含兩個compute units的硬體合成數據結果為共使用了約3600k個邏輯閘數量。

In addition to pursuing more shader cores for better rendering performance, another important trend in the evolution of modern graphic processing units (GPU) is to exploit their enormous computing power for general computing applications. This thesis has extended a past academic GPU design specialized for graphics rendering into a general embedded computing engine which can support massive data parallel processing. The proposed design is developed according to the platform and memory models defined in the framework of open computing language (OpenCL). Therefore, this thesis first clusters four shader cores together as a compute unit, and each core is regarded as a processing element which can communicate each other through the newly installed local memory. The overall compute engine is formed by multiple compute units, which can exchange messages through global memory. Its access is based on the same control mechanism used for texture processing in the original GPU design. In order to synchronize different threads executed on different processing elements, OpenCL defines the use of barrier which is also implemented in our design. The original GPU design has adopted the single instruction, multiple data (SIMD) processor architecture which may become inefficient since the ratio of vector instructions in general computing programs may not be too large. Therefore, our design has transformed the vector processor into scalar processor in order to achieve better hardware utilization. Furthermore , the special function unit is also separated from the arithmetic logic unit (ALU) to become a common resource shared by all processing elements in the same compute unit. The overall equivalent gate count of our design which comprises two compute units is about 3600k.

目錄
論文審定書 i
摘要 iii
Abstract iv
目錄 v
圖目錄 vii
Chapter 1概論 1
1.1研究動機 1
1.2 論文大綱 2
Chapter 2 研究背景與相關研究 3
2.1多核繪圖處理器 3
2.2 OpenCL 架構 5
2.3 Scalar運算處理器架構 6
2.4 同步處理 8
Chapter 3 平行運算處理器 10
3.1 向量指令集與純量處理器 10
3.1.1 向量指令集 10
3.1.2 Scalar運算處理器支援向量指令 13
3.1.2.1硬體的運作方式 15
3.2處理器硬體架構 16
3.2.1 Compute Unit中各模組功能 16
3.2.2 多核心運算單元(Multi_core) 19
3.2.3 Local Memory 存取機制 23
3.3 處理器流程 25
3.3.1 Warp在處理器中的排程 25
3.3.2 Work Item切換機制及硬體實作 26
3.3.3 存取Global Memory和Special Function指令 29
3.3.3.1 Global Memory指令 29
3.3.3.2 Special Function指令 33
3.3.4 Barrier指令 34
3.3.4.1硬體的運作方式 35
3.4設定平行處理器參數所使用到的使用者介面 37
Chapter 4 驗證方式及結果分析 39
4.1. EASY平台驗證 39
4.2 FPGA階層驗證 42
4.2.1 FPGA階層合成軟體及模擬環境 42
4.2.2 驗證結果 43
4.3 合成數據分析 45
Chapter 5結論與未來目標 47
5.1結論 47
5.2未來目標 47
參考文獻 48

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