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博碩士論文 etd-0808115-120610 詳細資訊
Title page for etd-0808115-120610
論文名稱
Title
階層式走訪之光線追蹤電路設計
Design of ray tracing circuit with hierarchical traversal
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
54
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-08-21
繳交日期
Date of Submission
2015-09-08
關鍵字
Keywords
包圍體階層、角錐剔除、階層式走訪、群組光線、光線追蹤
BVH, Frustum culling, Hierarchical traversal, Ray-tracing, Packet ray
統計
Statistics
本論文已被瀏覽 5656 次,被下載 144
The thesis/dissertation has been browsed 5656 times, has been downloaded 144 times.
中文摘要
在許多的嵌入式裝置中,快速的電腦圖學呈像已經變成了基本需求。光線追蹤可以藉由模擬現實生活中光線的彈射行為,繪製出比傳統基於深度緩衝區(depth-buffer)的呈像技術更加逼真的畫面品質,如何讓光線追蹤在嵌入式系統的環境中達到即時的呈像,成了最近幾年很熱門的話題。
為了加速光線追蹤的運算,本論文提出了一個演算法,能夠有效率地進行群組光線對樹狀結構的節點進行相交測試,藉由投影節點的axis-alignment bounding box (AABB)與群組光線角落四條的光線至xy、yz和zx平面,將相交測試變成二維空間的測試。軟體實驗結果可以顯示出,執行時間會比個別光線測試的方式節省40%。為了能夠進一步節省走訪樹狀結構的時間,本論文提出階層式走訪的方法,採用較大的群組光線進行走訪,當走訪至葉節點時,群族光線會拆成較小的子群組,對節點進行相交測試。由實驗結果可以表示,當要繪製出大型場景的一部份時,所提出階層式走訪的方式能夠有較佳的速度提升。
基於提出的演算法,本論文設計的光線追蹤加速電路主要由一個陰影光線產生器、兩個走訪測試單元及八個三角形相交測試單元組成,在TSMC的90nm製程下,合成面積為13,347,560〖μm〗^2,可以運行至171MHz工作頻率。
Abstract
Fast rendering of computer graphics has gradually become an essential requirement for many embedded electronic devices. Ray-tracing can render more realistic graphics than the conventional depth-buffer based approach by mimicking the natural law of light transmission. How to achieve real-time ray-tracing in embedded environments has become a hot topic in recent years. In order to accelerate ray-tracing process, this thesis first proposes an efficient algorithm to test if a packet of rays and a node of the object tree intersect. By projecting the axis-alignment bounding box (AABB) of the testing node and the four corner rays of the packet into xy, xz, and zx planes, the intersection test can be carried out in two-dimensional coordinate world. The experimental result of the software simulation shows that up to 40% of execution time can be saved compared with the direct packet-ray rendering approach. Next, in order to further save the tree traversal time, this thesis proposes a hierarchal traversal scheme which adopts larger packets to traverse the object tree. Once it traverses down to the leaf nodes, the packets will be recursively divided into small sub-packets for further packet and node intersection tests. Our experimental results show that when rendering a small portion of large scenes, the proposed hierarchical traversal approach can achieve better speed-up. Based on the proposed algorithm, the thesis has developed a ray-tracing acceleration circuit which mainly comprises of one shadow ray generator, two traversal units, and eight intersection units. It has been synthesized by TSMC 90nm technology. The overall area of the proposed design is about 13,347,560〖μm〗^2, and can run up 170 Mhz.
目次 Table of Contents
論文審定書 i
摘 要 iii
Abstract iv
CONTENTS v
圖表 vii
方程式 ix
Chapter 1 概論 1
1.1研究動機 1
1.2論文大綱 2
Chapter 2 研究背景與相關研究 3
2.1光線追蹤介紹 3
2.2 Bounding Volume Hierarchies(BVH)介紹 5
2.3光線群組追蹤介紹(Packet Ray) 8
2.4 Ray-Box Intersection介紹 9
2.5 Ray-Triangle Intersection介紹 11
2.6 相關Ray Tracing硬體設計 12
Chapter 3 光線走訪演算法 16
3.1 Frustum-AABB/OBB Intersection 16
3.2階層式光線追蹤 19
3.3軟體測試結果 20
Chapter 4 階層式光線追蹤電路設計 26
4.1硬體架構 26
4.2 處理單元 29
4.2.1 光線走訪單元(Traversal Unit) 29
4.2.1.1 有限狀態機控制(Finite State Machine) 30
4.2.1.2 光線走訪處理單元(Traversal Compute Unit) 31
4.2.2 三角形相交測試單元(Intersection Unit) 33
4.2.3陰影光線產生器(Shadow Ray Generator) 34
Chapter 5光線追蹤電路設計實驗結果 35
5.1 RTL驗證 35
5.2合成數據與效能比較 36
5.2.1硬體成本 36
5.2.2效能比較 36
Chapter 6結論與未來展望 38
參考文獻 41
參考文獻 References
[1] 林弘, “單一及群組光線混合追蹤之光線追蹤電路設計,”國立中山大學碩士論文,Jul.2014
[2] B. De Greve, “Reflections and refractions in ray tracing,” Nov. 2006.
[3] J. Schmittler, I. Wald, and P. Slusallek, “SaarCOR: a hardware architecture for ray tracing,” in Proc. of the Conference on Graphics hardware, Eurographics Association, Aire-la-Ville, Switzerland, pp. 27-36, 2002.
[4] J. Schmittler, S. Woop, D. Wagner, W.J. Paul, and P. Slusallek. “Realtime ray tracing of dynamic scenes on an FPGA chip,” in Proc. of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics hardware. ACM, New York, NY, USA, pp. 95-106, 2004.
[5] S. Woop, J. Schmittler, and P. Slusallek, “RPU: a programmable ray processing unit for realtime ray tracing,” in ACM SIGGRAPH 2005 Papers, ACM, New York, NY, USA, pp. 434-444, 2005.
[6] S. Woop, E. Brunvand, and P. Slusallek, “Estimating performance of a ray-tracing ASIC design,” IEEE Symposium on Interactive Ray Tracing 2006, Salt Lake City, UT, USA, pp.7-14, Sep. 2006.
[7] C. Chang, C. Lee, and S. Chien, “A 2.88mm2 50M-intersections/s ray-triangle intersection unit for interactive ray tracing,” A-SSCC '08. IEEE Asian Solid-State Circuits Conference 2008, Fukuoka, Japan, pp.181-184, Nov. 2008.
[8] J. Spjut, A. Kensler, D. Kopta, and E. Brunvand, “TRaX: a multicore hardware architecture for real-time ray tracing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.28, no.12, pp.1802-1815, Dec. 2009.
[9] H. Kim, Y. Kim, and L. Kim, “Reconfigurable mobile stream processor for ray tracing,” IEEE Custom Integrated Circuits Conference, pp.1-4, Sep. 2010.
[10] J. Nah, J. Park, C. Park, J. Kim, Y. Jung, W. Park, and T. Han. “T&I engine: traversal and intersection engine for hardware accelerated ray tracing,” in Proc. of the 2011 SIGGRAPH Asia Conference, ACM, New York, NY, USA, 2011.
[11] A.S. Nery, N. Nedjah, F.M.G. Franca, and L. Jozwiak, “A parallel ray tracing architecture suitable for application-specific hardware and GPGPU implementations,” 14th Euromicro Conference on Digital System Design, pp.511-518, Aug. 2011.
[12] W. Lee, Y. Shin, J. Lee, J. Kim, J. Nah, S. Jung, S. Lee, H. Park, and T. Han. “SGRT: a mobile GPU architecture for real-time ray tracing,” in Proc. of the 5th High-Performance Graphics Conference, ACM, New York, NY, USA, pp. 109-119, 2013.
[13] “Caustic professional” http://www.imgtec.com/caustic/
[14] “Bounding volume hierarchies” http://en.wikipedia.org/wiki/Bounding_volume_hierarchy
[15] “K-d Tree” http://en.wikipedia.org/wiki/K-d_tree
[16] S. Boulos, D. Edwards, J D. Lacewell, J. Kniss, J. Kautz, P. Shirley, and I. Wald. “Packet-based whitted and distribution ray tracing,” in Proc. of Graphics Interface, ACM, New York, NY, USA, pp. 177-184, 2007.
[17] J. Gunther, S. Popov, H.-P. Seidel, P. Slusallek, “Realtime ray tracing on GPU with BVH-based packet traversal,” IEEE Symposium on Interactive Ray Tracing, pp.113-118, Sep. 2007.
[18] A. Williams, S. Barrus, R.K. Morley, P. Shirley, “An efficient and robust ray–box intersection algorithm,” in Journal of Graphics Tools, pp.49-54, Jan. 2005.

[19] T. Möller, B.Trumbore, “Fast, minimum storage ray-triangle intersection,”in Journal of Graphics Tools, pp.21-28, Oct. 1997.
[20] J.-H. Nah, H.-J. Kwon, D.-S. Kim, C.-H. Jeong, J. Park, T.-D. Han, D. Manocha, and W.-C. Park, “RayCore: A ray-tracing hardware architecture for mobile devices,” ACM Transactions on Graphics, vol. 30, no. 6, 2014.
[21] U. Assarsson and T. Moller, “Optimized view frustum culling algorithms for bounding boxes,” Journal of Graphics Tools, vol. 5, pp. 9–22, 2000.
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