現今3D IC是近期極為熱門的話題之一，由於其晶片面積較小、降低功耗、提升可靠性等特性，而備受矚目。然而3D IC的技術仍有很多挑戰，例如：良率、散熱、測試…等，針對測試方面，我們的研究團隊已對3D IC測試提供了一個嶄新的測試架構，其名為可適性測試模組(Scalable Test Module, STM)。
現有的3D IC測試方法[7]-[10] 都是將待測晶粒(Die Under Test，DUT)加入可測試性設計與特殊硬體設計，因此對設計者來說，會有設計與佈局的負擔。但是STM將會以晶粒的方式與DUT一起整合，藉此降低3D IC所需的測試成本與解決測試存取的問題。另外STM選擇面積與pin腳數少於IEEE 1500的IEEE1149.1 (JTAG)測試標準包裝之DUT進行測試進行整合，以便進行測試存取與應用。
本論文將針對上一版本STM的測試進行效能分析後，發現STM在進行下載測試資料的時間佔整體測試時間的75%以上。因此本論文之STM增加一組資料傳輸的port以進行平行傳輸並將測試流程最佳化，使得測試時間與面積皆有明顯的下降。除此之外，由於考量到使用者可以利用Test Response進行錯誤診斷，因此額外增加了上傳所有待測電路Test Response的功能。本論文的STM經由TSMC 0.18 um製程合成後，相較於原本STM的面積由26923.88 um2下降至17124.31 um2，整體面積的下降率到達36.40%。
本論文使用ISCAS C2670、C7552、S38584標準電路和IWLS DMA標準電路做STM的驗證和測試時間分析，並與先前STM進行比較。由於最佳化後之STM控制方面較先前複雜，使操作頻率從原本的139MHz下降至111MHz，但是整體的測試時間還是有顯著的下降，測試時間下降平均有43.18%。

3D IC is one of the hot research topics recently due to its advantages of smaller chip area and lower power consumption. However, many challenges are also induced, such as yied, thermal effect, testing, etc. To address the testing issue, we presented a new test architecture, called scalable test module (STM), in our previous work.
The developed 3D IC test methods usually integrate design for testability circuitry to dies under test (DUT). This, however, would incur some overheads to design and layout processes. Different from the previous methods, STM will be fabricated as a separate die and will be integrated to a 3D IC design during the assembly stage for reducing the design and layout cost. To address test access and test application issues, STM accesses DUTs via IEEE 1149.1 (JTAG) Std. test wrappers that are less complicated than the IEEE 1500 Std.
After analyzing the test efficiency of our previous STM, we find that downloading test data dominates overall test time (over than 75%). Accordingly in this thesis we focus on optimizing test efficiency of STM. We increase one additional pair of data transmission port and optimize the test flow. Moreover, we also add the functionality of transferring complete test responses of all DUTs to facilitate fault diagnosis.
Synthesis results by the TSMC T18 process shows that the area overhead of STM decreased from 26923.88 um2 to only 17124.31um2 (36.40% reduction). We also analyze test time of the optimized STM by using the ISCAS C2670, C7552、S38584 and IWLS DMA circuits. Experimental results show that 43.18% reduction on test time can be achieved on average, compared with our previous STM.

摘要 I
ABSTRACT II
目錄 III
圖目錄 VI
表目錄 X
第一章 簡介 1
1.1 3D IC 概述 1
1.2 研究動機 2
1.3論文貢獻 4
1.4章節介紹 5
第二章 背景知識與相關研究 7
2.1 IEEE 1149.1 測試標準包裝 7
2.2可適性測試模組之介紹 14
2.2.1 STM之測試架構 14
2.2.2平行測試的支援 18
2.2.3廣播測試(Broadcast)的支援 19
2.2.4 STM硬體架構 20
第三章 可適性模組之測試時間最佳化 21
3.1 先前STM測試時間比例 21
3.2腳位最佳化 22
3.3操作流程與架構最佳化 23
第四章 可適性模組之功能最佳化 25
4.1功能最佳化 25
4.2 最佳化後可適性模組硬體架構 27
4.2.1 Download 28
4.2.2 Test Access Mechanism，TAM 31
4.2.3 Upload 39
4.2.4 Storage 40
4.3合成結果與分析 41
第五章 測試時間分析與比較 43
5.1各個運作流程的分析與比較 43
5.2上一版本測試時間分析 54
5.3本論文測試時間分析與上版本比較 57
5.3.1本論文測試時間分析 57
5.3.2測試時間比較 61
5.4實際電路測試時間與分析 63
第六章 FPGA驗證 66
6.1 FPGA相關介紹 66
6.2實驗環境 67
6.2.1FPGA實現方式 67
6.2.2 FPGA燒錄相關資訊： 70
6.3 實驗驗證 70
6.3.1發生錯誤立即停止 71
6.3.2發生錯誤繼續執行 73
6.3.3執行結果皆正確 75
第七章 結論與成果 76
參考文獻 77

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