隨著半導體製程的進步，電子元件尺寸可以有效的被縮小，使晶片更容易受到製造缺陷(defect)與製程飄移(process variation)的影響，而導致整體晶片良率偏低。另一方面，由於元件尺寸的縮小，使其臨界電壓也隨之減少，使電路對於軟性錯誤越來越敏感，進而影響了晶片的可靠度。
效能下降容忍(performance degradation tolerance)在近幾年中被提出來提升電路良率與穩定度。此概念的基礎在於電路中可能存在一種特殊錯誤，稱為效能下降錯誤(performance degrading fault, pdef)，此種錯誤僅會造成系統效能下降，並不會造成錯誤的運算結果。倘若系統的效能下降仍可被接受，則此晶片將可繼續使用，提升晶片之有效良率。
基於效能下降容忍本論文提出一嶄新快取記憶體架構，透過停用錯誤的儲存區塊及利用記憶體的階層關係，將功能性錯誤(functional error)轉換成效能下降錯誤。我們再更進一步透過錯誤修正碼(error correcting code, ECC)修正錯誤並檢測軟性錯誤，減緩錯誤所造成的效能下降程度，實現出可容忍製程缺陷與軟性錯誤之快取記憶體架構。考量到錯誤修正碼所帶來的龐大面積負擔，我們提出一設計方法將其所需之檢測位元(check bits)存放於快取記憶體既有的儲存空間，以降低整體面積消耗。此方法可減少約6.27%的硬體面積消耗 (從16.64%降低至10.27%)。
利用標準測試程式所進行之實驗結果說明當快取記憶體有1%的儲存區塊發生錯誤時，其效能下降最多僅約1%左右。當20%的儲存區塊中發生錯誤時，其效能下降平均為16.67%。然而若加入錯誤修正碼修正錯誤之考量，假設有錯區塊有10%的機率僅有單一錯誤而可被修正，其效能下降將可減緩至15.27%；若錯誤修正機率為50%，其效能下降可更減緩至8.72%；若錯誤有90%的機率可被修正，其效能下降可再減緩至僅有1.62%。

When the feature size of transistors becomes smaller, chips are more sensitive to process defects and variation, which may result in low yield and reliability.
In recent years, a yield and reliability improvement method is proposed, which is called performance degradation tolerance (PDT). The focus of this method is based on a particular type of fault, called performance degrading faults (pdef). This type of faults can’t cause functional errors at system outputs, but may result in system performance degradation. If defective chips contain only pdef with acceptable performance degradation, these chips are still marketable, thereby enhancing the effective yield.
In this thesis, we propose a new cache architecture based on PDT. In this architecture all functional errors in the storage part are transformed to pdef by disabling faulty blocks and retrieving the data from the next level of memories. In addition, error correcting code (ECC) is employed to correct and detect errors such that the proposed cache can tolerate hard and soft errors, and the incurred performance degradation can be mitigated. For the area concern, we store check bits in the existing storage cells to further lower the incurred area overhead. The logical synthesis results show that the area overhead is thus reduced by 6.27% (from 16.64% to10.27%).
Experimental results based on several large realistic benchmark programs show that the incurred performance degradation of the proposed cache is less than 1% when the fault density is 1%. The performance degradation is about 16.67% when the fault density is 20%. However this degradation can be mitigated to 15.27%, 8.72%, and 1.62% by our ECC mechanism when there are probabilities of 0%, 50%, and 90% that these errors can be corrected.

論文審定書 i
摘要 ii
Abstract iii
目錄 iv
圖次 vii
表次 ix
第一章 介紹 1
1.1 研究動機 1
1.2 貢獻 5
1.3 章節介紹 6
第二章 背景知識與相關背景 8
2.1 容錯設計 8
2.2 效能下降錯誤 9
2.3 快取記憶體之架構與存取機制 10
2.4 儲存區塊關閉與取代 14
2.5 備份快取記憶體(Replication cache) 17
2.6 影檢測法(Shadow checking) 18
2.7 錯誤修正碼(Error correcting code，ECC) 19
2.8 內建自我測試電路 20
2.9 模擬參數設定與執行效能跑分程式 21
2.10 本論文架構與過去研究之比較 23
第三章 可容忍製程缺陷之快取記憶體設計與實現 24
3.1 硬體架構 24
3.2 可容忍製程缺陷之快取記憶體架構讀取操作 25
3.3 可容忍製程缺陷之快取記憶體架構寫入操作 26
3.4 效能下降錯誤數量分析 27
3.5 硬體實現結果 28
3.6 效能下降結果分析 28
3.7 快取記憶體尺寸之可適性分析 30
第四章 可容忍製程缺陷與軟性錯誤之快取記憶體設計與實現 31
4.1 結合單錯修正雙錯檢測電路之PDT cache 31
4.1.1 基本概念 31
4.1.2 儲存區塊分類與好處 32
4.1.3 快取記憶體架構讀取操作 33
4.1.4 快取記憶體架構寫入操作 34
4.1.5 硬體架構 35
4.1.6 記憶體單元(Memory unit)架構說明 36
4.1.7 LRU修改 38
4.1.8 效能下降錯誤數量分析 39
4.1.9 硬體實現結果 40
4.1.10 效能下降結果分析 42
4.2 結合內嵌檢測位元的單錯修正雙錯檢測電路之PDT cache 44
4.2.1 儲存區塊減少對於快取記憶體效能之影響分析 45
4.2.2 記憶體單元(Memory unit)架構說明 46
4.2.3 LRU修改 48
4.2.4 效能下降錯誤數量分析 49
4.2.5 硬體實現結果 52
4.2.6 效能下降結果分析 52
第五章 總結 57
參考文獻 58

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