近年來許多研究者為了拉近處理器與記憶體的效能差距，嘗試將處理器與記憶體整合在同一晶片上，因而提出了記憶體處理器(PIM : Processor-in-Memory)這種新的計算機結構。針對此新架構，我們提出SAGE(Statement Analysis Group Evaluation)程式分析系統，分析轉換程式，使其能充分發揮此新架構中主處理器(P.Host)與記憶體處理器(P.Mem)的效能特性。本篇論文主要是探討SAGE系統中的權值評估機制 (Weight Evaluation Mechanism)和一個主處理器搭配多個記憶體處理器的工作排程機制(1H-nM Scheduling Mechanism) 。其中權值評估機制用來評估每一個工作區塊的主處理器和記憶體處理器之權重，工作排程機制則是根據這兩種權重來排程，以發揮PIM架構中兩種處理器的效能特性。本論文並提供上述模組之實作概述與分析測速程式(benchmarks)之效能結果。

In order to reduce the performance gap between the processor and the memory subsystem, many researchers attempt to integrate the processor and memory on a single chip in recent years. Therefore a new class of computer architecture: PIM (Processor-in-Memory) are investigated. For this class of architecture, we propose a new transformation and parallelizing system, SAGE, to achieve the benefits of PIM architectures by fully utilizing the capabilities of the host processor and memory processors in the PIM system. In this thesis, we focus on the weight evaluation mechanism and 1H-nM scheduling mechanism. The weight evaluation mechanism is used to evaluate the weights of P.Host and P.Mem for each task. The 1H-nM scheduling mechanism takes two different weights into account to exploit the advantages of two kinds of processors in the PIM system. The experimental results of above mechanisms are also discussed.

目 錄
中文摘要 …………………………………………………………………I
英文摘要 …………………………………………………………………II
目錄 ………………………………………………………………………III
圖目錄 ……………………………………………………………………IV
表格目錄 …………………………………………………………………V
第一章 簡介……………………………………………………………1
第二章 Flex RAM結構介紹……………………………………………5
第三章 SAGE系統之介紹………………………………………………7
第四章 權值評估機制和工作排程機制之設計與實作………………11
第4.1節 權值評估機制………………………………………11
第4.2節 工作排程機制………………………………………16
第五章 實驗結果………………………………………………………39
第六章 結論……………………………………………………………44
參考文獻 …………………………………………………………………45

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