近年來隨著向量圖形應用需求的增加，如何開發出高效能的嵌入式圖形呈像系統逐漸變的熱門。對於嵌入式裝置而言記憶體頻寬是非常有限的資源，因此記憶體存取的優化成為最關鍵的設計問題之一。為了達到更好的記憶體存取效率，本論文首先提出了一個在二維（2D）圖形呈像系統方面高效能的階層式掃描線緩衝區架構，透過應用了一個使用在三維（3D）圖形系統的快速緩衝區清除方法。掃描線緩衝區是用來決定圖形物件的內部區域。掃描線緩衝區的存取在圖形繪製過程當中相當密集而且為所有對記憶體頻寬需求中最主要的部分。本論文藉由使用一個額外的輔助緩衝區來標記掃描線緩衝區的每個區塊的狀態，此作法不僅可以使用較少的週期與資料傳輸數目有效地將清除掃描線緩衝區，而且可以顯著地加速環繞計數的累加過程。實驗數據顯示資料存取的數量可以減少65%以上，最佳的情況甚至可以減少到76%。因為使用全畫面掃描線緩衝區的容量並不小，往往會被放置在外部記憶體，所以本論文也考慮了使用掃描線緩衝區快取來減少向外部記憶體存取的需求。通過僅使用4個快取區塊，就能減少50%以上向外部記憶體存取的需求。本論文提出的掃描線緩衝區設計的其他顯著特徵是可以和三維圖形呈像中的深度緩衝區整合，透過共享相同的緩衝區電路以降低整體的設計成本。此外，輔助緩衝區可以進一步擴展到更多的層級而達到節省更多的資料存取數量。除了新的掃描線緩衝區設計以外，本論文還提出了一種反轉路徑順序的填色方法，可以避免那些被一個以上的路徑所包圍的像素做冗餘的存取記憶體動作。對於某些測試圖形而言，減少像素更新的數目可以達到50%。

With the increasing demand of vector graphics applications, how to develop an efficient embedded rendering system becomes a hot issue in recent years. For embedded environment where the memory bandwidth is a very constrained resource, the optimization of buffer access is one of the most critical design issues. In order to achieve better memory access efficiency, this thesis first presents an efficient hierarchical scan-line buffer architecture for two-dimensional (2D) graphics rendering systems by extending a fast buffer-clear method used in three-dimensional (3D) graphics systems. The scan-line buffer is used to determine the interior regions of graphics objects. It will be accessed intensively and consume the major part of the overall memory bandwidth during the graphics rendering process. By using an additional level of auxiliary buffer to denote the status of blocks of scan-line buffer entries, the proposed method can not only be able to clear the scan-line buffer efficiently with much less cycles and data transfer amount, but it can also accelerate the winding count accumulation process significantly. Our experimental results show that the number of data accesses can be reduced by more than 65%, the best case can even be reduced to 76%. Since the size of the whole-frame scan-line buffer is not small, very often the buffer will be placed off-chip. Therefore, the thesis also considers the use of scan-line buffer cache to reduce the off-chip buffer accesses. By using only four cache blocks, the number of off-chip access cycles can be reduced by more than 50%. The other salient features of the proposed scan-line buffer design is that it can be integrated with the depth buffer used in 3D graphics in order to reduce the overall cost by sharing the same buffer circuits. In addition, the auxiliary buffer can be further expanded into more levels of hierarchy to achieve more saving of data accesses. In addition to the new scan-line buffer design, the paper also proposes an inverse-path-order-filling approach which can avoid the redundant access for those pixels encircled by more than one path. For some test objects, the saving of pixel update number can be up to 50%

論文審定書……………………………………………………………………………i
摘要 ii
Abstract iii
Chapter 1 概論 1
1.1研究動機 1
1.2論文大綱 2
Chapter 2 二維繪圖呈像相關研究 3
2.1 OpenVG與繪圖管線化流程 3
2.2 OpenVG點陣化程序 4
2.2.1方案I – AET 排序法 7
2.2.2方案II – 掃描線緩衝區法 9
2.2.3方案III – 全畫面緩衝區法 10
2.3掃描線緩衝區方法求WC程序 10
2.4限制框 12
2.5掃描線緩衝區資料新編碼方式 14
2.6階層式掃描架構 15
Chapter 3 高記憶體效能的點陣化方法 17
3.1全畫面緩衝區法階層化 17
3.1.1分部環繞計數編碼方式 18
3.1.2分部環繞計數值錯誤解決方法 18
3.2延遲緩衝區清除機制 20
3.3限制框應用 23
3.4基於三階層式全畫面緩衝區點陣化架構 24
3.5基於快取(Cache)的全畫面緩衝區點陣化架構 27
3.6實驗結果 28
3.6.1二階層式全畫面緩衝區法實驗 29
3.6.2三階層式全畫面緩衝區法實驗 32
3.6.3基於快取的三階層式全畫面緩衝區法實驗 34
Chapter 4 反轉路徑順序填色法 37
4.1實作方式 38
4.2實驗結果 39
4.3應用探討 40
Chapter 5 結論與未來展望 41
5.1結論 41
5.2未來展望 41
參考文獻 42

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