記憶體在現今的系統晶片 (system-on-chip ,SoC) 上所扮演的角色越來越重要，並且佔去整體晶片中大部分的面積。由於系統的複雜度逐漸提升，對於能提供多讀寫埠的記憶體需求也隨著增加，雖然商業公司有提供可支援single-port與dual-port的記憶體產生器，然而在處理器的設計上往往需要可以支援同時多個讀取與寫入功能的記憶體，因此無法有效的使用在cell-based design flow。另一方面，漏電流功耗的問題對於現今記憶體設計也成為一個很嚴重的問題，隨著製程尺寸的下降與讀寫埠的增加，會讓漏電流所佔的比例逐漸上升。為了解決能支援多個讀寫功能的需求與加速設計流程的整合，本論文實作一個可支援多個讀寫功能的記憶體，在記憶體元件設計上採用了單端的讀寫埠來減少面積，並使用階層式字元線架構與預先充電控制電路來降低功耗，此外還加入了一些低功率的設計來減少漏電流功耗，最後透過混合訊號設計流程(Mixed-Signal Design Flow)將本論文的多讀寫埠記憶體實踐於本實驗室所開發的頂點處理器(Vertex Shader)之記憶體設計。

Memory design plays an important role in current system-on-chip (SoC) design because memory takes a significant portion of total area. As the complexity of processor cores increases, the support of multiple read/write ports becomes an important issue in memory design. Although current commercial standard cell library usually support multi-port memory generators, they are not very efficient in many SoC design and the number of supported read/write ports usually do not satisfy system requirement. Another important issue in memory design for portable systems is the leakage power which is becoming a critical issue in advanced process technologies. In this thesis, we present a low-leakage multi-port SRAM design and apply it to the design of register files in the vertex shader processor for 3D graphics applications. The multi-port SRAM design uses single-end read/write circuit to reduce area, hierarchical decoding to reduce dynamic power, and some additional circuits to reduce static leakage power. The proposed multi-port SRAM design is integrated with the vertex shader processor using mixed-signal design flow.

中文論文審定書 i
中文摘要 iii
Abstract iv
第1章 導論 1
1.1 研究動機 1
1.2 論文組織 2
第2章 相關文獻 3
2.1 傳統SRAM架構 3
2.2 傳統6T SRAM細胞元設計 7
2.3 SRAM穩定度分析 9
2.4 SRAM周邊電路設計 13
2.5 改善漏電流設計 19
第3章 多讀寫埠SRAM設計 25
3.1 傳統電路架構設計 25
3.2 SRAM細胞元設計 29
3.3 周邊電路設計 35
3.4 電路佈局設計 42
第4章 低功率之設計 48
4.1 本體偏壓 48
4.2 電源閘控 55
4.3 低功率SRAM佈局設計 61
4.4 數據分析與比較 63
第5章 繪圖處理器之應用 71
5.1 應用於Vertex Shader之記憶體實作 71
5.2 多讀寫埠SRAM設計之比較 78
5.3 低功率SRAM設計之比較 79
5.4 繪圖處理器記憶體設計之比較 81
第6章 結論與未來展望 82
參考文獻 83

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