我們提出有關能達到低功率消耗高速度的無電容式單電晶體動態隨機存取記憶體(Capacitorless One-Transistor Dynamic Random Access Memory, 1T-DRAM)之架構，使用環繞式閘極(Gate All Around, GAA)結合垂直本體通道區並修改製程搭配而形成溝槽(Pass-Way Trench and Vertical Channel Transistor)之電晶體；以及解決了自我對準問題的垂直之電流橋元件架構，搭配偏移功函數和High-K氧化層之技術，達到縮小操作偏壓的目的。
第一個元件相對於傳統的架構，最大的差異就是元件從平面變為垂直式的架構；再來為閘極的形態，元件使用環繞式閘極，使閘極對通道的控制力更強；而我們在通道下方製作了溝槽儲存區，最主要的優點是可以在不增加消耗空間並擁有可以控制大小的儲存空間；但在記憶體操作部分隨著集積密度增加使元件的間隔變小，記憶體會面臨到陣列干擾的問題，如何將干擾問題解決將是記憶體的一大挑戰，而我們將元件製作中的溝槽部分做了修改並形成改良的新溝槽，希望能藉由將氧化層的阻隔去減少受到干擾時偏壓能給它的影響。然而，以本架構的傳統去做比較，可程式編程視窗減少了12.86％和寫入速度則變慢了119.51%，但對於記憶體而言另一重要的性能，資料保持時間可以獲得大幅度的改善。
第二個元件主要是在研究功函數的改變，藉由加大功函數的方法去降低操作偏壓，使閘極引致汲極漏電流機制能夠運用在低操作偏壓之下。而本架構的傳統元件隔離氧化層有著無法對準的問題，我們將元件改為垂直通道並搭配蝕刻技術去克服本問題，不只能使用在低於1.2伏特，在干擾部分也具有相當好的表現。
於本文中除了性能外也注重功率消耗，近期內有學者研究發現在電路中有大量的功率消耗原因都在記憶體陣列的部分，而我們也試著挑戰國際半導體技術藍圖對記憶體的標準，設計元件在低偏壓操作之方向。而本篇論文探討了性能，也以ITRS作為標準去設計偏壓作為達到低功率高速度的方向。

In this thesis, we propose a Capacitor-less 1T-DRAM structure with the pass-way trench for High performance and Low Power application. We have improved the device fabrication process to form the pass-way trench of the structure which combines the Vertical Channel and the Gate-All-Around structure (PTVCT). And, we also propose a Vertical Channel 1T-DRAM structure with the workfunction offset technology and High-K Oxide (WOVCT) for solving the self-aligned problem and the scaling biasing.
First, the PTVCT is compared with that conventional lateral structure that the most of improvement is vertical structure. And then, the PTVCT combines the Gate-All-Around structure that it has high gate controllability. Finally, the PTVCT has the controllable trench region under the channel that it is able to reduce the consumption. However, the package density of memory array increases that it results the disturbance seriously by the high density. We use the modified process to form the pass-way trench, it reduce the disturbance of biasing by using the isolation oxide. Comparing the conventional of the trench, the programming window and the programming time are degraded that they are 12.86 % and 119.51 % respectively. But the retention time is longer than the conventional by the pass-way trench.
Second, the WOVCT uses the high workfunction to operate by using the Gate-Induced Drain-Leakage mechanism (GIDL). It results the GIDL mechanism is possible to operate for the low biasing by the workfunction offset. However, the process of lateral device is complexity in the isolation oxide process. We use the same etching technology to solve the self-aligned problem with the vertical structure. The WOVCT is able to operate below the 1.2 V and it has good disturbance immunity.
In conclusion, we care the performance and the power consumption. Recently, we know the operation of memory is large consumption. We follow the ITRS to design the scaling biasing for the low power application. According to the standard of ITRS, the performance of the memory is potential to achieve the High-Speed operation and the Low-Power application.

第一章　　　導 論 1
1.1 研究背景 1
1.2 論文回顧 4
1.2.1　水平式元件架構 4
1.2.2　垂直式元件架構 6
1.2.3　電流橋元件架構 13
1.3 動機 16
1.4 論文架構 17
第二章 操作原理 18
2.1 物理機制探討 18
2.2 無電容式單電晶體動態隨機存取記憶體寫入機制說明 19
2.2.1　撞擊游離機制 19
2.2.2　寄生BJT(Parasitic BJT)機制 21
2.2.3　閘極引致汲極漏電流機制 23
2.2.4　穿隧場效應電晶體操作機制 25
2.2.5　閘極引致汲極漏電流與撞擊游離整合機制 27
第三章 元件設計 29
3.1 元件模擬探討 29
3.1.1　PTVCT模擬製程 29
3.1.2　電流橋元件模擬製程 31
3.2 元件實際製程探討 33
3.2.1　電流橋元件實作製程 33
第四章 PTVCT元件之研究方法探討與結果討論 35
4.1　物理機制模型探討 35
4.2　PTVCT元件架構說明 38
4.3　PTVCT元件之基本電性討論 42
4.3.1　輸入特性曲線 42
4.3.2　輸出特性曲線 43
4.4　PTVCT元件之記憶體特性探討 45
4.4.1　PTVCT元件之操作方式 45
4.4.2　PTVCT元件之可程式規劃視窗 (Programming Window, PW) 46
4.4.3　PTVCT元件之資料保存時間 (Retention Time, RT) 48
4.4.4　PTVCT元件之操作速度探討 50
4.4.5　PTVCT元件之抹除電壓探討 53
4.4.6　PTVCT元件之最佳化探討 56
4.4.7　PTVCT元件之溫度變化探討 58
4.4.8　PTVCT元件之低功率模式探討 60
4.4.9　PTVCT元件之電路陣列干擾探討 63
4.4.10　PTVCT元件之干擾容忍度探討 66
4.5　PTVCT元件之記憶體邊際比較 68
第五章 電流橋元件研究與探討 69
5.1　研究結果探討 69
5.1.1　WOVCT元件之架構說明 69
5.2　WOVCT元件之基本電性討論 71
5.2.1　輸入特性曲線 71
5.2.2　輸出特性曲線 73
5.3　WOVCT元件之記憶體特性探討 76
5.3.1　WOVCT元件之操作方式 76
5.3.2　WOVCT元件之可程式規劃視窗 77
5.3.3　WOVCT元件之資料保存時間 81
5.3.4　WOVCT元件之操作速度探討 83
5.3.5　WOVCT元件之溫度變化探討 85
5.3.6　WOVCT元件之操作功率探討 89
5.3.7　WOVCT元件之電路陣列干擾探討 91
5.4　WOVCT元件之記憶體邊際比較 96
5.5　實作結果探討 97
5.5.1　元件光罩規劃與製作細節 97
5.5.2　元件特性量測 101
第六章 結論與未來展望 103
6.1　結論 103
6.2　未來展望 104
參考文獻 105
附錄 112
論文著作 115

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