在本論文中，我們提出三個具有高集積密度、低操作偏壓、高速度、製程步驟簡單之非傳統互補式金氧半反相器，第一個架構為N型及P型之橫向單向性雙極性絕緣閘極電晶體所組成(Complemetary LUBISTOR)，第二個架構為N型閘極控制N+-N-M電晶體及P型閘極控制M-P-P+電晶體所組成(Gated-N+NM/MPP+)，第三個架構為N型橫向單向性雙極性絕緣閘極電晶體(在此架構中命名為閘極控制N+-N-P+電晶體)及P型閘極控制P+-P-N+電晶體所組成(Gated-N+NP+/P+PN+)，在三個架構中的N型及P型電晶體分別取代原本傳統互補式金氧半 (CMOS)之負型金氧半電晶體(NMOS)驅動器及正型金氧半電晶體(PMOS)負載器。
根據模擬結果顯示，所提出三個架構在低操作偏壓下皆具有相當高的操作速度。架構一(Complemetary LUBISTOR)與架構三(Gated-N+NP+/P+PN+)組成之非傳統互補式金氧半反相器在操作偏壓VDD = 0.5 V時均有優良及正確的邏輯特性，且在七級環形震盪器操作中分別取得之最高頻率為22.98 GHz與9.13 GHz，較傳統互補式金氧半在相同操作偏壓與尺寸條件下分別增加近2.3K與1 K倍。而架構三(Gated-N+NP+/P+PN+)之傳遞延遲時間方面在相同操作偏壓與尺寸條件下較傳統互補式金氧半下降了55 %。此外，架構二(Gated-N+NM/MPP+)與架構三(Gated-N+NP+/P+PN+)在驅動器與負載器兩元件之間可共享摻雜區輸出節點，且為矽覆絕緣(SOI)結構，兩元件間無需做額外的淺溝槽隔離(STI)結構阻隔，相較於傳統互補式金氧半反相器，將可大幅的提升集積密度減少46.1 %的佈局面積來降低製程成本。

This paper present three feasible non-classical complementary metal oxide semiconductor (CMOS) inverter configurations. The first structure is composed of N-type Lateral Unidirectional Bipolar-type Insulated-gate Transistor (LUBISTOR) for driver transistor and P-type LUBISTOR for load transistor (Complemetary LUBISTOR). The secand structure is composed of Gated control N+-N-M for driver N-type transistor and Gated control M-P-P+ for load P-type transistor (Gated-N+NM/MPP+). The third structure is composed of Gated control N+-N-P+ for driver N-type transistor and Gated control P+-P-N+ for load P-type transistor (Gated-N+NP+/P+PN+).
According to the TCAD simulations, the three non-classical CMOS inverter structures we presented can operation for low power supply and high speed application. The first structure (Complemetary LUBISTOR) and the third structure (Gated-N+NP+/P+PN+) have excellent CMOS inverter characteristics at VDD = 0.5 V. Also, obtain 7-stages ring oscillator with a maximum operating frequency is 22.98 GHz in first structure and 9.13 GHz in third structure, that improve about 2.3K and 1K times compare to conventional CMOS at 0.5 V power supply respectively. The third structure exhibits the propagation delay time (TP) 55% lower than that of the conventional CMOS inverter. Besides, the layout area of the second structure (Gated-N+NM/MPP+) and the third structure is significantly reduced about 46.1% when compared with the conventional CMOS inverter due to the new CMOS inverter possesses a unique shared-contacting output node.

第一章　導論 1
1.1 研究背景 1
1.1.1 改變結構 3
1.1.2 改變材料 7
1.1.3 使用應力技術 10
1.2 動機 12
第二章　物理機制與元件操作原理 14
2.1 元件物理機制 14
2.1.1 穿隧場效電晶體(TFET)物理與操作機制 14
2.1.2 閘極控制N+-N-M/M-P-P+與N+-N-P+/P+-P-N+電晶體物理與操作機制 16
2.2 邏輯元件操作理論與原理 22
2.2.1 傳統互補式金氧半邏輯閘操作理論與原理 22
2.2.2 以N型LUBISTOR及P型LUBISTOR所構成之具共享摻雜區域互補式金氧半反相器 28
2.2.3 以閘極控制N+-N-M電晶體及閘極控制M-P-P+電晶體所構成之具共享摻雜區域互補式金氧半反相器 31
2.2.4 以閘極控制N+-N-P+電晶體及閘極控制P+-P-N+電晶體所構成之具共享摻雜區域互補式金氧半反相器 34
第三章　元件架構設計與製程步驟 37
第四章　電性討論與分析 40
4.1 元件模擬使用之物理模型說明 40
4.2 元件模擬結果分析與討論 41
4.2.1 N型LUBISTOR(閘極控制N+-N-P+電晶體)之負型金氧半元件 41
4.2.2 閘極控制P+-P-N+ (Gated-P+PN+)電晶體之正型金氧半元件 45
4.2.3 閘極控制N+-N-P+電晶體及閘極控制P+-P-N+電晶體所構成之具共享摻雜區域非傳統互補式金氧半反相器 49
4.2.4 具共享摻雜區域非傳統互補式金氧半反相器之雜訊邊界特性 50
4.3 閘極控制N+NP+/P+PN+互補式金氧半、閘極控制N+NM/MPP+互補式金氧半及互補式LUBISTOR比較 52
4.4 數位邏輯電路模擬與應用 57
4.4.1 反或閘(NOR Gate) 57
4.4.2 反及閘(NAND Gate) 59
4.4.3 全加器(Full adder) 61
4.4.4 環形震盪器(Ring Oscillator) 63
4.4.5 靜態隨機存取記憶體(Static Random Access Memory, SRAM) 64
4.5 環形震盪器操作頻率比較 71
4.6 傳遞延遲時間(Propagation delay time)與評量指標(FOM)比較 74
4.7 閘極控制N+NP+/P+PN+互補式金氧半與傳統互補式金氧半之佈局面積比較 81
4.8 閘極控制N+NP+/P+PN+互補式金氧半反相器之邏輯電路寬度補償探討 82
4.9 閘極控制N+NP+/P+PN+互補式金氧半反相器之偏壓微縮探討 93
4.10 元件實作結果與量測 96
第五章　結論與未來展望 100
5.1 結論 100
5.2 未來展望 101
參考文獻 102
附錄 109

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