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博碩士論文 etd-0810109-230024 詳細資訊
Title page for etd-0810109-230024
論文名稱
Title
降低平均時間或最壞時間的堆疊最佳化草稿記憶體分配器
A Stack-Optimized Scratchpad Memory Allocator for Reducing Either the Average-Case or the Worst-Case Execution Time
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
49
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-06-29
繳交日期
Date of Submission
2009-08-10
關鍵字
Keywords
最差執行時間、記憶體配置、平均執行時間、即時系統、草稿記憶體
memory allocation, WCET, ACET, scratchpad memory, real-time systems
統計
Statistics
本論文已被瀏覽 5728 次,被下載 1669
The thesis/dissertation has been browsed 5728 times, has been downloaded 1669 times.
中文摘要
草稿記憶體(scratchpad memory)常被用於嵌入式即時系統(embedded real-time system),它不同於快取記憶體(cache)透過記憶體管理單元(MMU)來存取資料,而是直接存取。在嵌入式即時系統中,草稿記憶體相較於快取記憶體,有兩個優點,一個優點是少了記憶體管理單元的面積、耗電,另一個優點則在於草稿記憶體可以準確的知道在執行時,哪些變數位於草稿記憶體當中,而快取記憶體則是決定於執行時間的變化,所以不能確定在真正執行時,哪些變數會位於快取記憶體當中,由於這樣的特性,草稿記憶體可以有效的計算出正確的最差執行時間(WCET),因此經常被利用在即時系統上。
這篇論文我們提出了一個新的記憶體配置方法,專門用於配置堆疊變數及全域變數於草稿記憶體上,同時,也是第一個提出把草稿記憶體中暫時不使用的非換變數(non-escaping variable)移出到靜態記體中,使得草稿記憶體的使用效率能夠提升的研究。
我們也是第一個把測量實驗數據(profiling)用在最佳化最差執行時間的記憶體配置上,先前的最佳化都是以平均執行時間(ACET)為目標。我們也是第一個記憶體分配器可以切換最佳化在平均執行時間或最差執行時間上,這一個特性對於軟式即時系統(soft real-time system)有極大的幫助。在先前的研究中,對於草稿記憶體的配置方法而言,通常是針對平均執行時間,只有一個研究是針對最差執行時間,而那個研究利用的是靜態最差執行時間分析器(static WCET analyzer),而靜態最差執行時間分析器在目前而言,其實並沒有被廣泛的運用,因為使用上的限制比較大,而且他們的研究只是針對最差執行時間的最佳化;相反的,我們的研究使用比較被廣泛利用的測量最差時間分析器(measurement-based WCET analysis),而我們的配置方法則是可以使用於平均執行時間或最差執行時間上,這一個性質對於利用於軟式即時系統上是相當重要的。
Abstract
Scratchpad memory (SPM) is popular for real-time embedded systems. Whereas caches use a memory management unit (MMU) to control which data accesses go to the fast, on-chip SRAM, SPM directly maps certain addresses to the SRAM. One advantage of SPM is that it avoids the cache’s costly MMU. Another advantage is that the SPM is 100% statically predictable, whereas the variables stored in the cache depend upon the dynamic execution history. This predictability is beneficial for real-time systems which must schedule tasks to finish by fixed deadlines. To set these deadlines, system designers must determine the worst-case execution times (WCETs) of the applications. The predictability of SPM makes these WCETs easier to measure.
This thesis presents a new method for allocating stack and global data to the SPM. It is the first method to make use of the special properties of non-escaping variables so as to increase the effective size of the SPM. Our insight is that many local variables of caller functions can be temporarily swapped out of the SPM while the callee function executes.
Ours is also the first method to support profiled WCET measurements in the allocation strategy. Most previous SPM methods optimize only for the average-case execution time (ACET), despite the fact that SPMs are often used in real-time environments where the WCET is also important. This new memory allocation strategy is also the first to be WCET/ACET tunable, a feature that is particular useful for soft real-time systems.
Only one previous work considers a WCET-targeted SPM allocator. That work, however, only applies to static WCET analysis tools. Such tools are difficult to program and are not widely used. Also, they only have application to the most safety-critical of real-time systems. In contrast, our approach is the first to employ measurement-based WCET analysis (such as is most commonly used in industry) for SPM allocation.
目次 Table of Contents
Acknowledgements.................................................................. i
摘要........................................................................................ ii
Abstract.................................................................................. iii
Contests................................................................................... v
List of Figures....................................................................... vii
Chapter 1 Introduction............................................................. 1
1.1 Scratchpad Memory (SPM).......................................... 2
1.2 Measuring the WCET and the ACET.......................... 2
1.2.1 Measurement-Based Analysis.................................. 2
1.2.2 Static Analysis.......................................................... 5

Chapter 2 Related Works......................................................... 7
2.1 Preventing Compiler Optimizations from Increasing the WCET.................................................................. 7
2.2 Developing New Compiler Methods Specifically for Improving the WCET................................................. 8
2.3 Compiler Methods that Improve WCET as a By-Product of Providing ACET Support to Hardware with Predictability................................................... 10
Chapter 3 Method Overview................................................. 13
3.1 WCET-Targeted Allocation...................................... 13
3.2 Allocation Algorithm................................................ 15
3.2.1 The Push Up/Down Method.................................. 23
3.2.2 A Method for Merging Costs................................. 26
3.2.3 Final Algorithm..................................................... 28
3.3 WCET/ACET Tune-able Allocation........................ 30

Chapter 4 Experiments and Discussion................................ 33
4.1 Simulations............................................................... 33
4.2 Results and Discussion............................................ 35

Chapter 5 Conclusion and Future Work................................. 38
Reference.............................................................................. 39
參考文獻 References
[1] R. Kirner and P. Puschner, “Classification of WCET Analysis Techniques”, in Proc. of the 8th IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC), Seattle, Washington, USA, May 2005.
[2] R. Kirner, I. Wenzel, B. Rieder, and P. Puschner, “Using Measurements as a Complement to Static Worst-Case Execution Rime Analysis”, Intelligent Systems at the Service of Mankind, vol.2, December 2005.
[3] R. Kirner, “Extending Optimising Compilation to Support Worst-Case Execution Time Analysis”, Ph.D. Thesis, Institut für Technische Informatik, Technischen Universität Wien, May 2003.
[4] J. Engblom, A. Ermedahl, M. Sjödin, J. Gustafsson, and H. Hansson, “Worst-Case
Execution Time Analysis for Embedded Real-Time Systems”, International Journal on
Software Tools for Technology Transfer, volume 4, p 437-455, 2003.
[5] Peter Puschner and Alan Burns, “A Review of Worst-Case Execution-Time Analysis”, Journal of Real-Time Systems, 18(2/3):115–128, May 2000.
[6] J. Wegener and M. Grochtmann, “Verifying Timing Constraints of Real-Time Systems by Mean of Evolutionary Testing”, Real-Time Systems, vol. 15, no. 3, p. 275-298, November 1998.
[7] P. Atanassov, “Experimental Assessment of Worst-Case Program Execution Times”, PhD Thesis, Technischen Universität Wien. May 2003.
[8] G. Bernat, A. Colin, and S. M. Petters, “WCET Analysis of Probabilistic Hard Real-Time Systems”, in Proc. of the 23rd Real-Time Systems Symposium (RTSS), Austin, Texas. Dec 2002.
[9] S. Edgar and A. Burns, “Statistical Analysis of WCET For Scheduling”, in Proc. of the 22rd Real-Time Systems Symposium (RTSS), London, United Kingdom. December 2002.
[10] R. Kirner and P. Puschner, “Classification of Code Annotations and Discussion of
Compiler-Support for Worst-Case Execution Time Analysis”, in Proc. of the 5th International Workshop on Worst-Case Execution Time Analysis, Palma, Spain. July 2005.
[11] J. Collins, S. Sair, B. Calder, and D. Tullsen, “Pointer Cache Assisted Prefetching”, in Proc. of the 35th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-35), Istanbul, Turkey, November 2002.
[12] Y. Zhang, S. Haga, and Rajeev Barua, “Execution History Guided Instruction Prefetching”, Journal of Supercomputing, volume 27 issue 2, p. 129-147. Kluwer Academic Publishers. February 2004.
[13] C. Healy, D. Whalley, and M. Harmon, “Integrating the Timing Analysis of Pipelining and Instruction Caching”, in Proc. of the 16th Real-Time Systems Symposium (RTSS), Pisa, Italy. pp.288-297. December, 1995.
[14] Kim, S., S. L. Min, and R. Ha, “Efficient Worst Case Timing Analysis of Data Caching”, in Proc. of the 2nd IEEE Real-Time Technology and Applications Symposium (RTAS), Boston, MA, USA, pp. 230-240. June 1996.
[15] Y. Li, S. Malik, and A. Wolfe, “Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches”, in Proc. of the 17th Real-Time Systems Symposium (RTSS), Washington, D.C., USA, December 1996.
[16] F. Mueller, “Generalizing Timing Predictions to Set-Associative Caches”, in Proc. of the 9th Euromicro Workshop on Real-Time Systems. Toledo, Spain, pp. 64-71. June 1997.
[17] T. Lundqvist, “A WCET Analysis Method for Pipelined Microprocessors with Cache Memories”, Technical Report, Department of Computer Engineering, Chalmers University of Technology, June 2002.
[18] H. Ramaprasad and F. Mueller, “Bounding Worst-Case Data Cache Behavior by
Analytically Deriving Cache Reference Patterns”, in Proc. of the IEEE Real-Time and
Embedded Technology and Applications Symposium (RTAS), San Francisco, California, March 2005.
[19] L. Thiele and R. Wilhelm, “Design for Timing Predictability”, Real-Time Systems, Volume 28 , Issue 2-3, pp 157-177, November-December 2004.
[20] G. Bernat and N. Hosti, “Compiler Support for WCET Analysis: a Wish List”, in Proc. Of the 3rd International Workshop on WCET Analysis (WCET), Porto, Portugal, July 2003.
[21] W. Zhao, B. Cai, D. Whalley, M. Bailey, R. van Engelen, X. Yuan, J. Hiser, J. Davidson, K. Gallivan, and D. Jones, “Vista: a System for Interactive Code Improvement”, in Proc. of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Berlin, Germany, 155–164. June 2002.
[22] H. Falk, P. Lokuciejewski, and H. Theiling, “Design of a WCET-Aware C Compiler”, in Proc. of the 6th International Workshop on Worst-Case Execution Time Analysis (WCET), Dresden, Germany, July 2006.
[23] S. Marlowe. “Safe Optimization for Hard Real-Time Programming”, in Special Session on Real-Time Programming, 2nd International Conference on Systems Integration, p. 438–446, Morristown, New Jersey. June 1992.
[24] D. Sandell, “Evaluating Static Worst-Case Execution Time Analysis for a Commercial Real-Time Operating System”, Master’s Thesis, Mälardalen University, Västerås, Sweden.2004.
[25] H. Falk and M. Schwarzer, “Loop Nest Splitting for WCET-Optimization and
Predictability Improvement”, in Proc. of the 4th IEEE Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Seoul, Korea, October 2006.
[26] S. Hong, and R. Gerber, “Compiling Real-Time Programs into Schedulable Code”, in Proc. of the ACM SIGPLAN '93 Conference on Programming Language Design and Implementation (PLDI), p. 166-176, Albuquerque, New Mexico, June 1993.
[27] S. Lee, J. Lee, C. Park, and S. Min. “A Flexible Tradeoff between Code Size and WCET Using a Dual Instruction Set Processor”, in International Workshop on Software and Compilers for Embedded Systems. Springer, Amsterdam, Netherlands, p. 244–258. September, 2004.
[28] P. Puschner, “Writing Temporally Predictable Code”, in Proc. of the 7th International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS), San Diego, California, p. 85-91. January 2002.
[29] J. Allen, K. Kennedy, C. Porterfield, and J. Warren, “Conversion of Control Dependence to Data Dependence”, in Proc. of the 10th ACM Symp. on Principles of Programming Languages, Austin, Texas, p. 177-189, January 1983.
[30] W. Zhao, P. Kulkarni, D. Whalley, C. Healy, F. Mueller, and G. Uh, “Tuning the WCET of Embedded Applications”, in Proc. of the IEEE Real-Time and Embedded Technology and Applications Symposium, Toronto, Canada, p. 472–480. May 2004.
[31] P. Kulkarni, W. Zhao, H. Moon, K. Cho, D. Whalley, J. Davidson, M. Bailey, Y. Paek, and K. Gallivan, “Finding Effective Optimization Phase Sequences”, in Proc. of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (CASES), San Diego, California, p. 12–23. October 2003.
[32] W. Zhao, D. Whalley, C. Healy, and F. Mueller, “WCET Code Positioning”, in Proc. of the IEEE Real-Time Systems Symposium, Lisbon, Portugal, p. 81–91. December 2004.
[33] W. Zhao, W. Kreahling, D. Whalley, C. Healy, and F. Mueller, “Improving WCET by Applying Worst-Case Path Optimizations”, Real-Time Systems, volume 34, issue 2, p. 129–152.October 2006.
[34] Vivy Suhendra, Tulika Mitra, Abhik Roychoudhury, and Ting Chen, “WCET Centric Data Allocation to Scratchpad Memory”, in Proc. Of the 26the IEEE International Real-Time Systems Symposium, Singapore, 2005
[35] Vivy Suhendra, Abhik Roychoudhury, and Tulika Mitra, “Scrathpad Allocation for
Concurrent Embedded Software”, in CODES+ISSS, Atlanta, Georgia, USA, October 2008
[36] L. Wehmeyer and P. Marwedel, “Influence of Onchip Scratchpad Memories on WCET Prediction”, in Proc. of the 4th International Workshop on Worst-Case Execution Time Analysis (WCET), Catania, Sicily, Italy, May 2004.
[37] V. Suhendra, C. Raghavan, and T. Mitra, “Integrated Scratchpad Memory Optimization and Task Scheduling for Mpsoc Architectures”, in Proc. of the Conference on Compilers, Architecture, and Synthesis for Embedded System (CASES), Seoul, Korea, October 2006.
[38] O. Avissar, R. Barua, and D. Stewart. “Heterogeneous Memory Management for
Embedded Systems”, in Proceedings of the ACM 2nd Int'l Conf. on Compilers, Architectures, and Synthesis for Embedded Systems (CASES), Atlanta, GA, November 2001.
[39] S. Udayakumaran, A. Dominguez, and R. Barua, “Dynamic Allocation for Scratch-Pad Memory Using Compile-Time Decisions”, ACM Transactions on Embedded Computing Systems (TECS), volume 5, issue 2, p. 472-511. May 2006.
[40] S. Debray and W. Evans, “Profile-Guided Code Compression”, in Proc. of the ACM
SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Berlin,Germany, p. 95-105, June 2002.
[41] A. Dominguez, S. Udayakumaran, and R. Barua, “Heap Data Allocation to Scratch-Pad Memory in Embedded Systems”, Journal of Embedded Computing (JEC), volume 1, issue 4, p.521-540, IOS Press, Amsterdam, The Netherlands, July 2005.
[42] Alfred V. Aho, Monica S. Lam, Ravi Sethi, and Jeffrey D. Ullman, “Static Allocation” in Compilers principles, techniques, & tools, New York, America, p. 518-520, 2007
[43] The MiBench Suite. http://www.eecs.umich.edu/mibench/.
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