在三維圖學呈像中，光線追蹤技術比起傳統的呈像技術，呈像畫面可以更為逼真。在不久將來，光線追蹤很可能成為下一個世代電腦圖學的主要技術，可以慢慢地應用在嵌入式系統上。然而，光線追蹤的呈像計算量是非常高，使用純軟體來實現是非常困難的。
因此本文提出了一種專用於光線追蹤的硬體設計。所提出的光線追蹤電路，主要由走訪單元、三角形相交測試以及陰影光線產生器所構成，將場景中的所有物件進行分類，以樹結構表示，來減少光線追蹤在呈像時的相交測試數量。因此，樹的走訪是整個光線追蹤運算的關鍵之一。本論文中，將提出單一及混合光線走訪單元，群組光線的走訪可以減少走訪測試數量，但是對於群組內的光線，如果不具備較好的相干性(coherence)，可能會導致光線與三角形相交測試數量增加。因此，本論文提出，主要光線和陰影光線使用群組光線，而其他次要光線則使用單一光線進行走訪。
本論文所提出的混合式光線走訪比單一光線走訪，節省了一半的時間;也比群組光線走訪方式節省超過40%的時間。如果場景中，產生出更多更複雜的次要光線，可以節省更多時間。本論文所提出的單一及群組光線混合追蹤之光線追蹤電路已經在SOPC(System-on-a-Programmable-Chip)平台上進行了驗證，硬體成本約720K個閘，並且在90nm製程下，可以運行至161MHz工作時脈。

Ray-tracing can render more realistic images than the traditional depth-buffer based rendering approach such that many people expect it can be gradually applied to embedded applications in near future. However, the computational complexity of ray-tracing rendering is very high such that it can hardly be realized by pure
software implementation. Therefore, this thesis proposed a dedicated ray-tracing hardware design. The proposed ray-tracing circuit is mainly composed of a traversal unit, an intersection unit, and a shadow-ray generator. For ray-tracing rendering, the graphics objects are usually represented in a tree structure in order to reduce the overall number of intersection tests. Therefore, the tree-traversal operation becomes a critical part of the entire ray-tracing process. In this thesis, a new travel unit has been proposed which is based on hybrid single and packet ray traversal technique. Packet-ray traversal can be used to reduce the ray-box intersection tests, but for those packets whose rays do not have good coherence property, it may lead to the increase of the ray-triangle intersection tests. Therefore, in our thesis, the primary rays and shadow rays will be traversed in packets, while the other secondary rays will be traversed individually.Our results show that the proposed hybrid traversal can save more than half of cycles compared with single ray traversal. It can still save more than 40% of executions cycles compared with pure packet-ray traversal. The saving may increase when more secondary rays are generated in the scene. Our ray-tracing circuit has been verified in a SOPC (System-on-a-Programmable-Chip) platform. The overall gate count is 720 K, and can run up to 161 MHz under 90 nm technology.

論文審定書 i
摘要 ii
Abstract iii
CONTENTS iv
List of Figure vi
List of Function viii
Chapter 1 概論 1
1.1研究動機 1
1.2論文大綱 2
Chapter 2 研究背景與相關研究 3
2.1光線追蹤介紹 3
2.2 Bounding Volume Hierarchies(BVH)介紹 6
2.3光線群組追蹤介紹(Packet Ray) 9
2.4 BVH Traversal介紹 11
2.5 Ray-Triangle Intersection介紹 13
2.6 相關Ray Tracing硬體設計 14
Chapter 3 混合追蹤之光線追蹤電路設計 18
3.1單一及群組光線混合追蹤 18
3.2硬體架構 20
3.3排程單元(Scheduler) 25
3.3.1紀錄表 25
3.3.2光線執行順序 29
3.4處理單元 30
3.4.1光線走訪單元(Traversal Unit) 30
3.4.1.1 有限狀態機控制(Finite State Machine) 31
3.4.1.2 光線走訪處理單元(Traversal Compute Unit) 34
3.4.2三角形相交測試單元(Intersection Unit) 35
3.4.2.1 有限狀態機控制(Finite State Machine) 36
3.4.2.2 三角形相交測試處理單元(Intersection Compute Unit) 38
3.4.3陰影光線產生器(Shadow Ray Generator) 40
Chapter 4實驗結果與分析 42
4.1驗證環境 42
4.1.1RTL驗證 42
4.1.2FPGA驗證 42
4.2實驗結果 43
4.2.1RTL成果展示 43
4.2.2FPGA成果展示 44
4.2.3效能比較 45
Chapter 5結論與未來展望 46
參考文獻 48

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