本篇論文提出一低功率及可以補償偏移電位的生醫信號記錄器和一低功率比較器。在記錄如身體之微小訊號時，需要經過一級高增益放大器後，才能達到數位類比轉換器所要求的輸入範圍。然而，在如此高增益放大的系統中，一些微小的偏移電位都有著使放大器飽合的可能，特別是那些隨著時間變化的偏移電位〈例如：電極移動〉可能導致記錄時發生空白部份。

此篇所提的系統可偵測放大器的輸出，並且當放大器輸出將離開其動態範圍時，重置輸出位準至放大器輸出動態範圍的中間點。而此系統的回授機制並非連續性的，可避免一般記錄系統使用濾波器的缺點。

此外，本篇論文所提的另一項為低功率、低偏移電壓比較器，採用低電流操作，藉以達到低功率的要求。而其平均消耗電流為130nA，偏移電壓為2mV。

這個系統已經採用台灣積體電路製造股份有限公司所提供的0.35μm 2P4M CMOS製程，來驗證模擬的結果。

This thesis presents a bio-signal recording system with offset cancellation and a low power comparator. The recording of bio-signal requires high-gain amplification before recording, to match the input to the range of the analog to digital converter (ADC); interference could be a problem if it causes the amplifier to reach saturation, leaving the recording inoperable (i.e., blank) until it returns to its normal state. The proposed system can monitor the amplifier output, and reset the amplifier output to a point near the center of its dynamic range before the amplifier output leaves its dynamic range. The proposed system provides discrete compensation voltages to cancel the offset voltage, and thereby avoids the shortcomings of conventional filters.

Furthermore, a low power and low offset voltage comparator for low current operation is proposed. It is suitable for the clock controller in a sampled bio-signal acquisition system. The measured current consumption of the comparator is less than 130 nA, and the offset voltage is 2 mV.

The proposed recording system and comparator have been implemented in the TSMC (Taiwan Semiconductor Manufacturing Company) 0.35μm 2P4M CMOS process technology to verify the simulation results as well as the correctness of the proposed architecture.

Abstract III

Chapter 1 Introduction 1
1.1 Basic concept 1
1.2 Conventional recording system 2

Chapter 2 Proposed system 5
2.1 System description 5
2.2 Circuit description of proposed system 7
2.3 Simulation results 21
2.4 Layout of proposed system 27
2.5 Measurement 28
2.5.1 Measurement setup 28
2.5.2 Measurement results 29
2.6 Post-processing 34
2.7 Summary 36

Chapter 3 Low Power Comparator 37
3.1 Introduction 37
3.2 Block diagram 37
3.3 Circuit diagram 38
3.4 Simulation results 39
3.5 Layout of proposed comparator 44
3.6 Summary 45

Chapter 4 Conclusions and Future Work 46

References 48

List of Publications 50

Appendix 50

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