本篇論文主要在於探討當具有修正誤差能力之比較器式切換式電容電路被使用在以循環式redundant-sign-digit (RSD) 為演算法的類比數位轉換器時，其誤差修正的理論根據以及分析、電路的實作設計、模擬結果討論以及實作晶片的測量結果。
在切換式電容電路中，電容的不匹配一直是一個不可控制的因素。因此，從典型的比較器式切換式電容電路發展出一種具有修正誤差能力之比較器式切換式電容電路被設計出來，以解決電容不匹配所帶來的誤差。本文中敘述了將修正誤差功能加入比較器式切換式電容電路後所帶來的影響，還有誤差修正的操作機制。誤差修正的功能讓比較器式切換式電容電路具有增益可調以及參考電位可調的功能，並藉此修正電容不匹配所帶來的增益誤差以及位移誤差。此電路是以台灣積體電路製造股份有限公司的0.35μm 2-poly 4-metal CMOS 製程技術所製作。並以Cadence Spectre 以及HPSICE 線上模擬器做模擬驗證的工作。最後，本
文也記錄了實際晶片測量與模擬器模擬的結果比較。

This thesis focuses on the analysis theory, circuit design, simulations, and chip measurements of the transfer stage in the continuously error-trimming comparator-based switched-capacitor charge transfer stage in the cyclic redundant-sign-digit (RSD) algorithm.
Capacitor mismatching remains an insurmountable factor for switched-capacitor circuit designers. To correct errors which result from the capacitor mismatching, a continuous error-trimming circuit is generalized from a typical CBSC circuit. The
analysis theory of the error-trimming operation describes the effects of the error-trimming circuit in the CBSC circuit, as well as the guidelines for trimming. The error-trimming operation is able to tune the gain and virtual condition of the charge transfer stage for canceling the gain and offset errors. The circuit is designed, with the 0.35μm 2-poly 4-metal TSMC process, in fully integral circuits. The circuit is
simulated by a matlab simulator and an online Cadence Spectre simulator, to confirm how the operation works. Finally, chip measurements are recorded for verification and simulation comparisons.

Acknowledgements.........................................................................................................i
摘要................................................................................................................................ii
Abstract....................................................................................................................... iii
List of Figures ..............................................................................................................iv
Table of Contents..........................................................................................................vi
Chapter 1. INTRODUCTION................................................................................1
Chapter 2. BACKGROUND..................................................................................4
2.1. The Basic Concept of an Analog-to-Digital Converter .................................4
2.2. Redundant-Signed-Digit Cyclic Conversion Algorithm.................................5
2.3. Opamp-Based Switched-Capacitor charge transfer stage.............................6
2.4. Comparator-Based Switched-Capacitor charge transfer stage.....................9
Chapter 3. THEORY OF ERROR-TRIMMING IMPLEMENTATION.........14
3.1. Basic Characteristics and Analysis of the Analog-to-Digital Converter.....14
3.2. Error-Trimming Comparator-Based Switched-Capacitor Charge Transfer
Operation .................................................................................................................15
3.3. Analysis of the Error-Trimming Theory.......................................................20
Chapter 4. CIRCUIT DESIGN OF ERROR-TRIMMING CBSC STAGE.....25
4.1. CSDA Comparator.......................................................................................25
4.2. Clock Tree ....................................................................................................27
4.3. Current Source .............................................................................................30
vii
Chapter 5. RESULTS............................................................................................33
5.1. Simulation Results........................................................................................33
A. Matlab Simulation ...............................................................................................................33
B. Cadence Simulation.............................................................................................................35
5.2. Experiment results........................................................................................38
Chapter 6. CONCLUSION AND FUTURE WORKS .......................................47
6.1. Conclusion ...................................................................................................47
6.2. Future Works ................................................................................................47
REFERENCES...........................................................................................................49

[1] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A ratio-independent algorithm
analog-to-digital technique,“ IEEE J. Solid-State Circuits, vol. SC-19, pp. 828-836,
Dec. 1984.
[2] S. Lewis, H. Fetterman, G. Gross, R. Pamachandran, “A 10bit 20MS/s
Analog-to-Digital Converter,“ IEEE J. Solid- State Circuits, vol. 27, pp. 351-358, Mar.
1992.
[3] B. Ginetti, Paul G. A. Jespers, and André Vandemeulebroecke, “A CMOS 13-b
Cyclic RSD A/D Converter,” IEEE J. Solid-State Circuits, vol. 27. No. 7. July. 1992.
[4] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H. S. Lee,
“Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies,”
IEEE J. Solid-State Circuits, vol. 41. No. 12. Dec. 2006.
[5] K. Hwang, Computer Arithmetic—Principles, Architecture and Design. New
York: Wiley, 1979.
[6] Y.J. Kook, J. Li, B. Lee, and Un-Ku Moon, “Low-Power and High-Speed
Pipelined ADC Using Time-Aligned CDS Technique,” IEEE Custom Integrated
Circuits Conference (CICC), 2007.
[7] P. E. Allen, D. R. Holberg, “CMOS Analog Circuit Design,” 2nd edition, Oxford
University Press, 2002
[8] E. J. Siragusa, L. Galton, “Gain Error Correction Technique for Pipelined
Analog-to-Digital Converters,” Electronics Letters, vol. 36, No. 7, pp. 617-618, 2000.
[9] L. Brooks, H.-S. Lee, “A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC,”
IEEE J. Solid-State Circuit, vol. 42, No. 12, pp. 2677-2687, 2007.
50
[10] S. Manen, L. Royer, P. Gay, “A custom 12-bit cyclic ADC for the
electromagnetic calorimeter of the International Linear Collider,” IEEE Nuclear
Science Symposium Conference Record, 2008.
[11] H. Zhang, Q. Li, and E. Sánchez-Sinencio, “Minimum current/area
implementation of cyclic ADC,” Electronics Letters, vol. 45, No. 7, 26th March 2009.
[12] D. Garrity and P. Rakers, “A 10 bit, 2MS/s, 15mW BiCMOS Cyclic RSD A/D
Converter,” IEEE BCTM 12.2, 1996.