Title page for etd-0811109-143534


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URN etd-0811109-143534
Author Li-Shen Chang
Author's Email Address m963010126@student.nsysu.edu.tw
Statistics This thesis had been viewed 4725 times. Download 1 times.
Department Electrical Engineering
Year 2008
Semester 2
Degree Master
Type of Document
Language English
Title Comparator-Based Cyclic Analog-to-Digital Conversion with Error-Trimming
Date of Defense 2009-07-23
Page Count 60
Keyword
  • CBSC
  • error trimming
  • cyclic ADC
  • cyclic analog-to-digital
  • Abstract This thesis focuses on the analysis theory, circuit design, simulations, and chip measurements of the transfer stage in the continuously error-trimming comparator-based switched-capacitor charge transfer stage in the cyclic redundant-sign-digit (RSD) algorithm.
    Capacitor mismatching remains an insurmountable factor for switched-capacitor circuit designers. To correct errors which result from the capacitor mismatching, a continuous error-trimming circuit is generalized from a typical CBSC circuit. The
    analysis theory of the error-trimming operation describes the effects of the error-trimming circuit in the CBSC circuit, as well as the guidelines for trimming. The error-trimming operation is able to tune the gain and virtual condition of the charge transfer stage for canceling the gain and offset errors. The circuit is designed, with the 0.35μm 2-poly 4-metal TSMC process, in fully integral circuits. The circuit is
    simulated by a matlab simulator and an online Cadence Spectre simulator, to confirm how the operation works. Finally, chip measurements are recorded for verification and simulation comparisons.
    Advisory Committee
  • Jia-Jin Chen - chair
  • Tsang-Ling Hsu - co-chair
  • Jih-Ching Chiu - co-chair
  • Robert Rieger - advisor
  • Files
  • etd-0811109-143534.pdf
  • indicate in-campus access in a year and off_campus not accessible
    Date of Submission 2009-08-11

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