在製程的持續進步之下，單一系統級晶片裡面包含了數百萬個邏輯閘，可測試性的設計變得越來越重要，多掃瞄樹的測試架構可以有效地降低測試時間與測試資料，節省測試成本。目前二維架構的系統級晶片中，交連線已是延遲與功率消耗的主要因素，減少交連線長度成為非常重要的議題，而三維晶片利用直通矽晶穿孔技術，將多個晶片垂直堆疊，可以有效的降低內部交連線長度、降低功\\率消耗和提供異質整合等功能，已成為相關產業與學術界研究的方向。在本論文研究中，我們在三維晶片中同時考量繞線長度與掃瞄輸出限制的多掃瞄樹合成演算法，希望可以降低使用多掃瞄樹測試架構所需要的測試成本。

In the process of continuous scaling improvement under a single system-on-chip which contains millions of logic gates, testability of the design becomes more and more important and thus multiple scan tree test architecture can effectively reduce test time and test data simultaneously. In the current two-dimensional structure of the system-level chip, the interconnect has become one of the main factors in delay and power consumption, and thus optimizing interconnect becomes a very important topic. Especially, three-dimensional ICs, stacked multiple chips vertically by through-silicon-via technique, can be effective in reducing the length of the interconnects, power consumption and offering features of heterogeneous IC integration. In this research study, we consider three-dimensional chips in both respects of wire length and the scan output limits, and propose the test synthesis algorithm of multiple scan trees to reduce test cost for three dimensional integrated circuits.

List of Tables iii

List of Figures iv

Chapter 1 簡介 1
1.1 研究動機 1
1.2 論文貢獻 4
Chapter 2 研究背景 6
1.1 三維晶片 6
2.2 平行掃瞄樹測試壓縮架構 10
Chapter 3 建構掃瞄樹演算法 14
3.1 Phase I: 二維晶片分割為三維晶片&切割晶片指派至三維晶片階
層 (2D to 3D Partition & Tier Assignment) 15
3.1.1 二維晶片分割為三維晶片 (2D to 3D Partition) 15
3.1.2 切割晶片指派至三維晶片階層 (Tier Assignment) 17
3.2 Phase II: 建立相容群 (Compatible Group Construction) 21
3.3 Phase III: 掃瞄樹建構 (Scan Tree Construction) 23
3.4 Phase V: 階層間之連接&散置單元連接 (Level-to-Level Physical
Connection & Scatter Cell Connection) 28
3.4.1 階層間之連接 (Level-to-Level Physical Connection) 28
3.4.2 散置掃瞄單元連接 (Scatter Cell Connection) 29
Chapter 4 實驗結果 31
4.1 實驗環境 31
4.2 實驗結果分析 32
4.2.1 與二維晶片之比較 32
4.2.2 與三維晶片之比較 42
Chapter 5 結論 47

[1] X. Wu, P. Falkenstern, K. Chakrabarty, and Y. Xie, 「Scan-chain design and optimization for three-dimensional integrated circuits,」 ACM J. Emerg. Technol. Comput. Syst., vol. 5, no. 2, Article 9, July. 2009.
[2] K. S.-M. Li, and J.-Y. Hung, 「Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization,」 in Proc.IEEE Asian Test Symp., pp. 63-68, Nov. 2008.
[3] S.-J. Wang, X.-L. Li, and K. S.-M. Li, 「Layout-aware multi-layer multi-level scan tree synthesis,」 in Proc.IEEE Asian Test Symp., pp. 129-132, Nov. 2007.
[4] X. Wu, F. P., and Y. Xie, 「Scan chain design for three-dimensional integrated circuits (3D ICs),」 in Proc. Int. Conf. on Computer Design, pp. 208-214, Oct. 2007.
[5] K. Rahimi, and M. Soma, 「Layout driven synthesis of multiple scan chains」 IEEE Trans. Comput.-Aided Design, vol. 22, no. 3, pp. 317-326, Mar. 2003.
[6] K.S.-M. Li, Y.-C. Hung and J.-Y. Hung, 「Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint,」 IEEE Trans.Comput.-Aided Design, vol. 29 , no. 4, pp. 618-626 , Apr. 2010.
[7] Jin-Tai Yan; Zhi-Wei Chen; Dun-Hao Hu,「 Timing-driven Steiner tree construction for three-dimensional ICs」, in Proc. IEEE Circuits and Systems and TAISA
Conference., pp.335-338, June. 2008.
[8] Pathak, M., Sung Kyu Lim, 「 Performance and Thermal-Aware Steiner Routing for 3-D Stacked ICs」, in Proc. IEEE Trans. on Comput.-Aided Design, vol. 28, no. 9, pp. 1373-1386, Sept. 2009.
[9] Industrial Technology Research Institute, www.itri.org.tw
[10] SAMSUNG Semiconductor, http://www.samsung.com
[11] Institute of Microelectronics (IME), http://www.ime.a-star.edu.sg
[12] J.Munkres,「Algorithms for the assignment and transportation problems,」 Journal of the Society for Industrialand Applied Mathematics, vol. 5, no. 1, pp.32-38, Mar.1957.
[13] H.W.Kuhn, 「The hungarian method for the assignment problem,」 Naval Research
Lo-gistic Quarterly, vol. 2, pp. 83-97, 1955.
[14] G. Karypic, and V.Kumar. hMetis: a hypergraph partitioning package.
Available on WWW at URL: http://www.cs.umn.edu/~karypis/metis/hmetis
[15] K. D. Boese, A. B. Kahng, and R. S. Tsay, 「Scan chain optimization: Heuristic and optimal solutions,」 in UCLA CS Dept., Oct. 1994.
[16] N. Dev, S. Bhatia, S. Mukherjaa, S. Genova, and V. Kadam, 「A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain
Crossings」 in Proc. Int. Conf. on VLSI Design, pp. 187-193, Jan. 2008.
[17] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures, Morgan Kaufmann Publishers, 2006.
[18] Y. Bonhomme, et. al., 「An efficient scan tree design for test time reduction,」 in Proc. European Test Symp., pp. 174-179, May. 2004.
[19] S. Banerjee, D.R. Chowdhury, B.B. Bhattacharya, 」An efficient scan tree design for compact test pattern set,」 IEEE Trans. Comput.-Aided Deign, vol. 26, no. 7, pp.1331-1339, July. 2007.
[20] A. Chandra and K. Chakrabarty, 「Test data compression and test resource partitioning for system-on-a-chip using frequency directed run-length (FDR) codes,」
IEEE Trans. Computers, vol. 52, no. 8, pp. 1076-1088, Aug. 2003.
[21] S.M. Reddy, K. Miyase, S. Kajihara, and I. Pomeranz, 「On test data volume reduction for multiple scan chain designs,」 in Proc. VLSI Test Symp., pp. 103-108, Apr. 2002.
[22] A. Chandra and K. Chakrabarty, 「System-on-a-chip test-data compression and decompression architectures based on Golomb codes,」 IEEE Trans. Computer.-Aided Design, vol. 20, no. 3, pp. 355-368, Mar. 2001.
[23] P.-C. Tsai and S.-J. Wang, 「Multi-mode-segmented scan architecture with
layout-aware scan chain routing for test data and test time reduction,」 IET Computer Digital Techniques, vol. 2, no. 6, pp. 434-444, Nov. 2008.
[24] C.-A . Chen, S. K. Gupta , 「Efficient BIST TPG Design and Test Compaction via Input Reduction, 」 IEEE Trans. Comput.-Aided Deign, vol. 17, no. 8, pp. 692-705, Aug. 1998.
[25] K.Miyase, S.Kajihara, 「 Optimal scan tree construction with test vector modification fortest compression,」 in Proc Asian Test Symposium, pp. 136-141, Nov. 2003.
[26] K. Miyase, S. Kajihara, S. M. Reddy, 「Multiple scan tree design with test vector modification,」in Proc. Asian Test Symposium, pp. 76-81, Nov. 2004.